Multiple control stores for a pipelined microcontroller

Claim 2

A microcontroller for controlling a digital device said microcontroller comprising: at least three control memories each for storing a set of miroinstructions, each microinstruction being formed of a control field for controlling said digital device, a jump address field specifying the location in another control memory of the next microinstruction to be executed should a jump to subroutine or a return from subroutine be required and an instruction field specifying whether that particular microinstruction is a jump microinstruction, return microinstruction or requires neither action; at least three address registers one for each control memory to address the corresponding control memory for the next microinstruction to be fetched; means for fetching said microinstructions from each of said control memories in every clock cycle; an instruction register coupled to the respective memories and said digital device for receiving the control field and instruction field of one of said microinstructions fetched from said control memories; a multiplexer coupled between said instruction register and said control memories to select the instruction field of one of the microinstructions being fetched from said respective control memories; interconnection means coupled between each of said control memories and the address register of said another control memory for supplying a jump address to said address register of said another control memory; logic means coupled to said instruction field portion of said instruction register and to said address registers to specify one of said registers as a program counter, one of said registers as a jump address register and one of said address registers as a return from subroutine register; means responsive to said logic means to increment said program counter, to load a new address into said jump address register and to keep said return from subroutine register current contents; and push-down stack means coupled to said address registers to receive one or more return from subroutine addresses in a first-in last-out manner to accommodate the execution of a series of nested subroutines.

Claim 3

A microcontroller according to claim 1 wherein: each of said control memories contain the same sets of microinstructions.

Claim 4

A microcontroller according to claim 1 further including: a plurality of multiplexers, one between each of said address registers and said jump address outputted from said another control memory, said multiplexers also being coupled to an outside source of microinstruction addresses.

Claim 5

A microcontroller according to claim 1 wherein: each address register is a register counter that can be incremented to fetch, in order, a sequence of microinstructions from its corresponding control memory.

Claim 6

A microcontroller according to claim 1 further including: timing means coupled to the respective address registers and memories so that a microinstruction control field is supplied to said instruction register each clock time.

Claim 7

A microcontroller for controlling a digital device, said microcontroller comprising: at least three control memories each for storing a set of microinstructions, each microinstruction being formed of a control field for controlling said digital device, a jump address field specifying the location in another control memory of the next microinstruction to be executed should a jump to subroutine or a return from subroutine be required and an instruction field specifying whether that particular microinstruction is a jump microinstruction, return microinstruction or requires neither action; at least three address registers one for each control memory to address the corresponding control memory for the next microinstruction to be fetched; means for fetching said microinstructions from each of said control memories in every clock cycle; an instruction register coupled to the respective memories and said digital device for receiving the control field and instruction field of one of said microinstructions fetched from said control memories; a multiplexer coupled between said instruction register and said control memories to select the instruction field of one of the microinstructions being fetched from said respective control memories; interconnection means, coupled between each of said control memories and the address register of said another control memory for supplying a jump address to the address register of said another control memory; condition select means for receiving a condition signal from said digital device specifying that a conditional branch is required in the execution of a sequence of said microinstructions; logic means coupled between said condition select means and said plurality of address registers to select which control memory supplies the next microinstruction upon receipt of a condition signal from said digital device; means responsive to said logic means to increment said program counter, to load a new address into said jump address register and to keep said return from subroutine register current contents; and push-down stack means coupled to said address registers to receive one or more return from subroutine addresses in a first-in last-out manner to accommodate the execution of a series of nested subroutines.

Claim 8

A microcontroller for controlling a digital device, said microcontroller comprising: at least three control memories each for storing a set of microinstructions, each microinstruction being formed of a control field for controlling said digital device, a jump address field specifying the location in another control memory of the next microinstruction to be executed should a jump to subroutine or a return from subroutine be required and an instruction field specifying whether that particular microinstruction is a jump microinstruction, return microinstruction or requires neither action; at least three address registers one for each control memory to address the corresponding control memory for the next microinstruction to be fetched; means for fetching said microinstructions from each of said control memories in every clock cycle; an instruction register coupled to the respective memories and said digital device for receiving the control field and instruction field of one of said microinstructions fetched from said control memories; a multiplexer coupled between said instruction register and said control memories to select the instruction field of one of the microinstructions being fetched from said respective control memories; interconnection means, coupled between each of said control memories and the address register of said another control memory for supplying a jump address to the address register of said another control memory; condition select means for receiving a condition signal from said digital device specifying that a conditional branch is required in the execution of a sequence of said microinstructions; logic means coupled between said condition select means and said plurality of address registers to select which control memory supplies the next microinstruction upon receipt of a condition signal from said digital device; means responsive to said logic means to increment said program counter, to load a new address into said jump address register and to keep said return from subroutine register current contents; and push-down stack means coupled to said address registers to receive one or more return from subroutine addresses in a first-in last-out manner to accommodate the execution of a series of nested subroutines.

Claim 9

A microcontroller according to claim 6 wherein: each of said control memories contain the same sets of microinstructions.

Claim 10

A microcontroller according to claim 6 further including: a plurality of multiplexors, one between each of said address registers and said jump address outputted from said another control memory, said multiplexors also being coupled to an outside source of microinstruction addresses.

Claim 11

A microcontroller according to claim 6 wherein: each address register is a register counter that can be incremented to fetch, in order, a sequence of microinstructions from its corresponding control memory.