Method and apparatus for speeding up the determination of a microinstruction address in a data processing system

Claim 3

The method of claim 1 further comprising addressing the memory in response to the branch address contained in the branch register and reinitializing the address register using the address contained in the branch register in response to the test on the bits in the test register indicating a branch.

Claim 4

The method of claim 2 wherein the memory is addressed by the address contained in the address register in response to the test on the bits in the test register indicating there is to be no branch.

Claim 5

The method of claim 1 wherein the memory is addressed by the address contained in the address register in response to the test on the bits in the test register indicating there is to be no branch.

Claim 6

The method of claim 1 wherein one of the test bits in the test register is selected for testing in response to a predetermined portion of the microinstruction loaded into the microinstruction register.

Claim 7

The method of claim 5 wherein the test is performed by comparing the selected bit with a predetermined bit of the microinstruction loaded into the microinstruction register.

Claim 8

Apparatus for determining the address of a next microinstruction in a data-processing apparatus, the address determination being performed on the basis of the address and content of the immediately preceding microinstruction, comprising memory means for storing the microinstructions at addressable locations, an address register for storing addresses of the memory means, a branch register for storing addresses of the memory, a microinstruction register for storing the microinstruction read from an addressed location of the memory means, a test register for storing test bits, means for selectively coupling addresses contained by either the address register or the branch register to address inputs of the memory means, a logic control unit for controlling the selecting means in response to the value of at least one bit of a microinstruction contained in the microinstruction register and at least one test bit in the test register, the selected test bit being determined by a particular region of the microinstruction contained in the microinstruction register, said means for selectively coupling including means for simultaneously loading: (i) testing bits into the test register, and (ii) a microinstruction from the memory means into the microinstruction register; and means for thereafter simultaneously: (i) testing the bits contained in the test register, (ii) loading the branch register with a branch address derived either from the microinstruction register or from an external member, and (iii) incrementing the contents of the address register for the memory means by one unit, and means for selecting the branch register or the address register in response to a test carried out on the bits contained in the test register for fetching from the memory means the microinstruction situated at the address located either in the branch register or in the address register, depending upon which is selected, as the address for the microinstruction to be read from the memory means, whereby the microinstruction situated at the selected address is supplied from the memory means to the microinstruction register.

Claim 9

Apparatus for determining the address of a next microinstruction in a data-processing apparatus, the address determination being performed on the basis of the address and content of the immediately preceding microinstruction, comprising memory means for storing the microinstructions at addressable locations, an address register for storing addresses of the memory means, a branch register for storing addresses of the memory, a microinstruction register for storing the microinstruction read from an addressed location of the memory means, a test register for storing test bits, means for selectively coupling addresses contained by either the address register or the branch register to address inputs of the memory means, a logic control unit for controlling the selecting means in response to the value of at least one bit of a microinstruction contained in the microinstruction register and at least one test bit in the test register, the selected test bit being determined by a particular region of the microinstruction contained in the microinstruction register, said means for selectively coupling including means for simultaneously loading: (i) testing bits into the test register, and (ii) a microinstruction from the memory means into the microinstruction register; and means for thereafter simultaneously: (i) testing the bits contained in the test register, (ii) loading the branch register with a branch address derived either from the microinstruction register or from an external member, and (iii) incrementing the contents of the address register for the memory means by one unit, and means for selecting the branch register or the address register in response to a test carried out on the bits contained in the test register for fetching from the memory means the microinstruction situated at the address located either in the branch register or in the address register, depending upon which is selected, as the address for the microinstruction to be read from the memory means, whereby the microinstruction situated at the selected address is supplied from the memory means to the microinstruction register.

Claim 10

The apparatus of claim 7 wherein the selecting means comprises a multiplexer.

Claim 11

The apparatus of claim 8 wherein outputs of the branch register are connected in parallel to inputs of the address register and to inputs of a first channel of a two-channel multiplexer, inputs of a second channel of the two-channel multiplexer being connected to outputs of the address register.

Claim 12

The apparatus of claim 9 further including means for controlling the two channel multiplexers in response to a control signal derived from the logic control unit in response to said test bits and a test bit contained in the microinstruction having the same value.

Claim 13

The apparatus of claim 7 wherein outputs of the branch register are connected in parallel to inputs of the address register and to inputs of a first channel of a two-channel multiplexer, inputs of a second channel of the two-channel multiplexer being connected to outputs of the address register.

Claim 14

The apparatus of claim 11 further including means for controlling the two channel multiplexers in response to a control signal derived from the logic control unit in response to said test bits and a test bit contained in the microinstruction having the same value.

Claim 15

The apparatus of claim 7 wherein the selecting means comprises a two channel multiplexer and further including means for controlling the two channel multiplexers in response to a control signal derived from the logic control unit in response to said test bits and a test bit contained in the microinstruction having the same value.

Claim 16

Apparatus for determining a microinstruction address in response to the address and content of a immediately preceding microinstruction, comprising: memory means for storing microinstructions at addressable locations, an address register for storing addresses of the memory means, a branch register for storing addresses of the memory means, a microinstruction register for storing the microinstruction read from an addressed location of the memory means, a test register for storing test bits, means for simultaneously loading: (i) testing bits into the test register, and (ii) a microinstruction from the memory means into the microinstruction register, means for thereafter simultaneously: (i) testing the bits contained in the test register, (ii) loading the branch register with a branch address derived either from the microinstruction register or from an external member, and (iii) incrementing the contents of the address register for the memory means by one unit, and means for selecting the branch register or the address register in response to a test carried out on the bits contained in the test register for fetching from the memory means the microinstruction situated at the address located either in the branch register or in the address register, depending upon which is selected, as the address for the microinstruction to be read from the memory means, whereby the microinstruction situated at the selected address is supplied from the memory means to the microinstruction register.

Claim 17

Apparatus for determining a microinstruction address in response to the address and content of a immediately preceding microinstruction, comprising: memory means for storing microinstructions at addressable locations, an address register for storing addresses of the memory means, a branch register for storing addresses of the memory means, a microinstruction register for storing the microinstruction read from an addressed location of the memory means, a test register for storing test bits, means for simultaneously loading: (i) testing bits into the test register, and (ii) a microinstruction from the memory means into the microinstruction register, means for thereafter simultaneously: (i) testing the bits contained in the test register, (ii) loading the branch register with a branch address derived either from the microinstruction register or from an external member, and (iii) incrementing the contents of the address register for the memory means by one unit, and means for selecting the branch register or the address register in response to a test carried out on the bits contained in the test register for fetching from the memory means the microinstruction situated at the address located either in the branch register or in the address register, depending upon which is selected, as the address for the microinstruction to be read from the memory means, whereby the microinstruction situated at the selected address is supplied from the memory means to the microinstruction register.

Claim 18

The apparatus of claim 14 further including means for selecting one of the test bits in the test register in response to a predetermined portion of the microinstruction loaded into the microinstruction register.

Claim 19

The apparatus of claim 15 further including means for performing the test by comparing the selected bit with a predetermined bit of the microinstruction loaded into the microinstruction register.

Claim 20

The apparatus of claim 14 further including means for testing the bits in the test register, said selecting means being responsive to the testing means.