Microprogrammed computer control unit capable of efficiently executing a large repertoire of instructions for a high performance data processing unit

Claim 2

A data processing system for performing data manipulations under the control of instructions, said system including buffer storage apparatus, instruction processing apparatus and instruction execution apparatus, said instructions being processed in a pipelined fashion by said instruction processing apparatus during a number of different successive phases of operation to completion, said instruction processing apparatus comprising: a plurality of registers for storing instructions to be processed received from said buffer storage apparatus, each instruction including an operation code having a first number of bits; a first addressable control store coupled to a first one of said plurality of registers for receiving signals corresponding to an operation code of an instruction to be processed, said first control store including a plurality of locations, each for storing a word including at least a control sequence code and an address, said control sequence code including a second number of bits which is less than said first number of bits coded for specifying one of a number of hardwired control sequences and said address identifying a first microinstruction of a different one of a plurality of execution sequences and an output register connected to said store for storing the word contents of a location specified by said operation code; control sequence decode circuit means coupled to said first control store output register for decoding signals corresponding to said control sequence code; and, hardware control sequencing means coupled to said sequence decode circuit means for generating sequences of control signals in response to said signals for defining the operations to be performed during selected ones of said different successive phases; said first control store being conditioned in response to said signals corresponding to each operation code of an instruction stored in said first register to read out the contents of a predetermined one of said plurality locations into said first control store output register and said decode circuit means in response to said control sequence code conditioning said hardware control sequencing means for generating a predetermined sequence of said control signals for enabling the completion of the operations of as many of said selected ones of said different successive phases under hardwired control before transferring control to said first microinstruction of one of said plurality of execution sequences specified by said address read out from said predetermined location of said first control store.

Claim 3

The system of claim 1 wherein said processing apparatus further includes: a cycled addressable second control store including a plurality of locations storing at least one microinstruction of a different one of said plurality of execution sequences required for executing the operation specified by said operation code during a last one of said phases of operation; an address register connected to receive said address from said first control store output register and connected to said second control store for read out of the microinstruction contents during a cycle of operation; and an output register connected to said second control store for temporarily storing said microinstruction contents read out during said cycle of operation, said hardware control sequencing means generating signals upon completing said predetermined sequence for transferring said address to said address register for read out of said one microinstruction of said execution sequence to complete execution of the operation specified by said operation code during said last one of said phases of operation.

Claim 4

The system of claim 2 wherein said hardware control sequence means further includes: instruction cycle control means connected to said decode circuit means for generating signals corresponding to sequences of control states defining the sequences of operations to be performed by said processing apparatus during said first one of said phases; and, hardware logic decode circuit means coupled to said instruction cycle control means and to said first control store output registers, said cycle control means being conditioned by said decode circuit means to generate signals corresponding to a first predetermined one of said sequences of control states for conditioning said hardward logic decode circuit means to generate said control signals during the cycles of operation defined by the control states of said first predetermined one of said sequences.

Claim 5

The system of claim 3 wherein said hardware logic decode circuit means includes circuits for generating signals for causing a next instruction to be fetched from said buffer storage apparatus and loaded into said first one of said plurality of registers.

Claim 6

The system of claim 3 wherein certain ones of said instructions have a single word format including an address which can be coded to specify that certain types of indirect address modifications be performed upon the address included therein, said cycle control means being conditioned by said control sequence decode circuit means and signals from said instruction address to generate signals corresponding to a second predetermined one of said sequences of control states for conditioning said hardward logic decode circuit means to generate control signals for conditioning said processing apparatus to perform the specified indirect address modification under hardwired control in response to said control signals.

Claim 7

The system of claim 3 wherein certain ones of said instructions have a multiword format including a plurality of addresses, said cycle control means being conditioned by said control sequence decode circuit means and signals from each instruction address to generate signals corresponding to a third predetermined one of said sequences of control states for conditioning said hardware logic decode circuit means to generate control signals for conditioning said processing apparatus to perform those operations required for fetching the different operands specified by each of said plurality of addresses under hardwired control in response to said control signals.

Claim 8

The system of claim 6 wherein those operations include operations required for generating an indirect operand address when any one of said instruction addresses is coded to specify an indirect operand address operation.

Claim 9

The system of claim 7 wherein each instruction includes at least one address, said different successive phases of processing including an instruction cycle (I cycle) wherein instruction operand addresses are generated, a cache cycle (C cycle) wherein said buffer storage apparatus fetches an operand specified by said instruction address and an execution cycle (E cycle) wherein the manipulations specified by the instruction operation code to be performed upon said operand are executed by said processing apparatus and wherein said first one of said phases corresponds to said I cycle.

Claim 10

The system of claim 8 wherein said hardward logic decode circuit means includes buffer command decode circuit means, said buffer command decode circuit means being conditioned by said control sequence code and said signals from said cycle control means to generate coded buffer command signals for forwarding to said buffer storage apparatus for fetching said operand specified by said instruction address as required for the execution of said instruction during said C cycle phase of operation.

Claim 11

The system of claim 9 wherein said processing apparatus further includes a memory request decoder circuit coupled to said buffer command decode circuit means, said request decoder circuit being only conditioned by certain codings of said buffer command signals to generate a memory request signal for signaling said buffer storage apparatus to perform a C cycle of operation thereby enabling said C cycle of operation to be bypassed in accordance with the coding of said control sequence code.

Claim 12

The system of claim 10 wherein said control sequence code indicating an instruction within an effective address class conditions said buffer command decode circuit means to generate command signals specifying a direct memory operation and said request decoder circuit in response to said command signals being inhibited from generating said memory request signal.

Claim 13

The system of claim 1 wherein said plurality of locations of said first control store includes a number of different groups of locations, each location containing a control sequence code coded to have the same bit pattern for specifying the same predetermined one of said hardwired sequences of control signals for executing a different instruction of a class of instructions corresponding in number to the number of locations within a corresponding one of said groups associated therewith.

Claim 14

The system of claim 12 wherein a number of said different groups of locations contain control sequence codes coded to have bit patterns specifying a number of hardwired control sequences executable within a limited number of cycles of operation whereby said instruction execution by said instruction processing apparatus proceeds primarily under hardwired control.

Claim 15

The system of claim 13 wherein said number of hardwired control sequences include a first group of sequences executable within one cycle of operation by said instruction processing apparatus, said first group including a load single sequence of operation during which said buffer storage apparatus is directed to execute a read single memory cycle of operation.

Claim 16

The system of claim 13 wherein said number of hardwired control sequences include a second group of sequences executable within two cycles of operation by said instruction processing apparatus, said second group including a load double sequence of operation during which said buffer storage apparatus is directed to execute a read double memory cycle of operation.

Claim 17

The system of claim 13 wherein a number of said different groups of locations contain control sequence codes coded to have bit patterns specifying another number of hardwired sequences of control signals requiring more than said limited number cycles of operation.

Claim 18

The system of claim 16 wherein said another number of hardwired control sequences of operation include a store double sequence.

Claim 19

A data processing system including a microprogrammed data processing unit for performing data manipulations under the control of instructions wherein the processing of each instruction proceeds in a number of different successive phases of operation, said processing unit comprising: a plurality of registers for storing instructions to be processed, each instruction including a multibit operation code; a first addressable store coupled to a first one of said plurality of registers for receiving signals of the operation code of a next instruction to be processed, said store including a plurality of locations, each for storing a word including at least a multibit control sequence code, said multibit control sequence code consisting of a smaller number of bits than said multibit operation code coded for specifying one of a number of hardwired control sequences, different groups of said locations storing multibit control sequence codes having the same bit pattern; an output register connected to said store for storing the word contents of a location read out in response to said operation code; control sequence decode circuit means coupled to said output register for generating signals resulting from decoding said multibit control sequence code; and, hardwired control sequencing means coupled to said sequence decode circuit means, said hardwired control means being conditioned by said signals from said decode circuit means to generate a predetermined sequence of control signals for defining the series of operations within a number of successive cycles of operation required to be performed for completing the operations of as many of said phases of instruction processing under hardwired control before switching said microprogrammed data processing unit to operate under microprogram control.

Claim 20

A data processing system including a microprogrammed data processing unit for performing data manipulations under the control of instructions wherein the processing of each instruction proceeds in a number of different successive phases of operation, said processing unit comprising: a plurality of registers for storing instructions to be processed, each instruction including a multibit operation code; a first addressable store coupled to a first one of said plurality of registers for receiving signals of the operation code of a next instruction to be processed, said store including a plurality of locations, each for storing a word including at least a multibit control sequence code, said multibit control sequence code consisting of a smaller number of bits than said multibit operation code coded for specifying one of a number of hardwired control sequences, different groups of said locations storing multibit control sequence codes having the same bit pattern; an output register connected to said store for storing the word contents of a location read out in response to said operation code; control sequence decode circuit means coupled to said output register for generating signals resulting from decoding said multibit control sequence code; and, hardwired control sequencing means coupled to said sequence decode circuit means, said hardwired control means being conditioned by said signals from said decode circuit means to generate a predetermined sequence of control signals for defining the series of operations within a number of successive cycles of operation required to be performed for completing the operations of as many of said phases of instruction processing under hardwired control before switching said microprogrammed data processing unit to operate under microprogram control.

Claim 21

The data processing system of claim 18 wherein each location of said first control store further includes an address field for identifying a first microinstruction of a different one of a plurality of execution sequences.

Claim 22

The system of claim 19 wherein said processing apparatus further includes: a cycled addressable second control store including a plurality of locations storing at least one microinstruction of a different one of said plurality of execution sequences required for executing the operation specified by said operation code during a last one of said phases of operation; an address register connected to receive said address from said first control store output register and connected to said second control store for read out of the microinstruction contents during a cycle of operation; and an output register connected to said second control store for temporarily storing said microinstruction contents read out during said cycle of operation, said hardware control sequencing means generating signals upon completing said predetermined sequence for transferring said address to said address register for read out of said one microinstruction of said execution sequence to complete execution of the operation specified by said operation code during said last one of said phases of operation.

Claim 23

The system of claim 20 wherein said hardware control sequencing means further includes: instruction cycle control means connected to said decode circuit means for generating signals corresponding to sequences of control states defining the sequences of operations to be performed by said processing apparatus during said first one of said phases; and, hardware logic decode circuit means coupled to said instruction cycle control means and to said first control store output registers, said cycle control means being conditioned by said decode circuit means to generate signals corresponding to a first predetermined one of said sequences of control states for conditioning said hardware logic decode circuit means to generate said control signals during said hardwired cycles of operation defined by the control states of said predetermined sequence.

Claim 24

The system of claim 21 wherein said system further includes buffer storage apparatus coupled to said processing unit and wherein said hardware logic decode circuit means includes circuits for generating signals for causing a next instruction to be fetched from said buffer storage apparatus and loaded into said first one of said plurality of registers.

Claim 25

The system of claim 21 wherein certain ones of said instructions have a single word format including an address which can be coded to specify that certain types of indirect address modifications be performed upon the address included therein, said cycle control means being conditioned by said control sequence decode circuit means and signals from said instruction address to generate signals corresponding to a second predetermined one of said sequences of control states for conditioning said hardware logic decode circuit means to generate control signals for conditioning said processing apparatus to perform the specified indirect address modification under hardwired control in response to said control signals.

Claim 26

The system of claim 21 wherein certain ones of said instructions have a multiword format including a plurality of addresses, said cycle control means being conditioned by said control sequence decode circuit means and signals from each instruction address to generate signals corresponding to a third predetermined one of said sequences of control states for conditioning said hardware logic decode circuit means to generate control signals for conditioning said processing apparatus to perform those operations required for fetching the different operands specified by each of said plurality of addresses under hardwired control in response to said control signals.

Claim 27

The system of claim 24 wherein each instruction includes at least one address, said different successive phases of processing including an instruction cycle (I cycle) wherein instruction operand addresses are generated, a cache cycle (C cycle) wherein said buffer storage apparatus fetches an operand specified by said instruction address and an execution cycle (E cycle) wherein the manipulations specified by the instruction operation code to be performed upon said operand are executed by said processing apparatus and wherein said first one of said phases corresponding to said I cycle.

Claim 28

The system of claim 25 wherein said hardware logic decode circuit means includes buffer command decode circuit means, said buffer command decode circuit means being conditioned by said control sequence code and said signals from said cycle control means to generate coded buffer command signals for forwarding to said buffer storage apparatus for fetching said operand specified by said instruction address as required for the execution of said instruction during said C cycle phase of operation.

Claim 29

The system of claim 26 wherein said processing apparatus further includes a memory request decoder circuit coupled to said buffer command decode circuit means, said request decoder circuit being only conditioned by certain codings of said buffer command signals to generate a memory request signal for signaling said buffer storage apparatus to perform a C cycle of operation thereby enabling said C cycle of operation to be bypassed in accordance with the coding of said control sequence code.

Claim 30

The system of claim 27 wherein said control sequence code indicating an instruction within an effective address class conditions said buffer command decode circuit means to generate command signals specifying a direct memory operation and said request decoder circuit in response to said command signals being inhibited from generating said memory request signal.

Claim 31

The system of claim 28 wherein a number of said different groups of locations contain control sequence codes coded as having bit patterns specifying a number of hardwired control sequences executable within a limited number of cycles of operation whereby said instruction execution by said processing unit proceeds primarily under hardwired control.

Claim 32

The system of claim 29 wherein said number of hardwired control sequences include a first group of sequences executable within one cycle of operation, said first group including a load single sequence during which said buffer, storage apparatus is required to execute a read single memory cycle of operation.

Claim 33

The system of claim 29 wherein said number of hardwired control sequences include a second group of sequences executable within two cycles of operation by said processing unit, said second group including a load double sequence during which said buffer storage apparatus is directed to execute a read double memory cycle of operation.

Claim 34

The system of claim 29 wherein a number of said different groups of locations contain control sequence codes coded to have bit patterns specifying another number of hardwired sequences of control signals requiring more than said limited number cycles of operation.

Claim 35

The system of claim 32 wherein said another number of hardwired control sequences include a store double sequence of operation.

Claim 36

A data processing system including a cache unit for storing information including data and instructions and a microprogrammed processing unit for performing data manipulations under the control of instructions wherein the processing of instructions proceed in a pipelined fashion wherein each instruction is processed in a number of different successive phases of operation to completion, said microprogrammed processing unit comprising: a plurality of registers for storing instructions to be processed received from said cache unit, each instruction including an operation code having a first number of bits; a first addressable control store coupled to a first one of said plurality of registers for receiving signals corresponding to the operation code of an instruction to be processed, said first control store including a plurality of locations, each for storing a word including at least a control sequence code and an address, said control sequence code including a second number of bits which is less than said first number of bits coded for specifying one of a number of hardwired control sequences and said address identifying a first microinstruction of a different one of a plurality of execution sequences and an output register connected to said store for storing the word contents of a location specified by said operation code; a cycled addressable second control store including a plurality of locations storing at least one microinstruction of a different one of said plurality of execution sequences required for executing the operation specified by said operation code during a last one of said phases of operation; an address register connected to receive said address from said first control store output register and connected to said second control store for read out of the microinstruction contents during a cycle of operation; an output register connected to said second control store for temporarily storing said microinstruction contents read out during said cycle of operation, said hardware control sequencing means generating signals upon completing said predetermined sequence for transferring said address to said address register for read out of said one microinstruction of said execution sequence to complete execution of the operation specified by said operation code during said last one of said phases of operation; control sequence decode circuit means coupled to said first control store output register for decoding signals corresponding to said control sequence code; and, hardware control sequencing means coupled to said sequence decode circuit means for generating sequences of control signals for defining the operations to be performed during selected ones of said phases of instruction processing; said first control store being conditioned in response to said signals corresponding to each operation code of an instruction stored in said first register to read out the contents of a predetermined one of said plurality locations into said first control store output register and said decode circuit means in response to said control sequence code condtioning said hardware control sequencing means for generating a predetermined sequence of said control signals for enabling the completion of the operations of as many of said selected ones of said different successive phases under hardwired control before transferring control to said one microinstruction of one of said execution sequences of said second control store specified by said address read out from said predetermined location of said first addressable store.

Claim 37

A data processing system including a cache unit for storing information including data and instructions and a microprogrammed processing unit for performing data manipulations under the control of instructions wherein the processing of instructions proceed in a pipelined fashion wherein each instruction is processed in a number of different successive phases of operation to completion, said microprogrammed processing unit comprising: a plurality of registers for storing instructions to be processed received from said cache unit, each instruction including an operation code having a first number of bits; a first addressable control store coupled to a first one of said plurality of registers for receiving signals corresponding to the operation code of an instruction to be processed, said first control store including a plurality of locations, each for storing a word including at least a control sequence code and an address, said control sequence code including a second number of bits which is less than said first number of bits coded for specifying one of a number of hardwired control sequences and said address identifying a first microinstruction of a different one of a plurality of execution sequences and an output register connected to said store for storing the word contents of a location specified by said operation code; a cycled addressable second control store including a plurality of locations storing at least one microinstruction of a different one of said plurality of execution sequences required for executing the operation specified by said operation code during a last one of said phases of operation; an address register connected to receive said address from said first control store output register and connected to said second control store for read out of the microinstruction contents during a cycle of operation; an output register connected to said second control store for temporarily storing said microinstruction contents read out during said cycle of operation, said hardware control sequencing means generating signals upon completing said predetermined sequence for transferring said address to said address register for read out of said one microinstruction of said execution sequence to complete execution of the operation specified by said operation code during said last one of said phases of operation; control sequence decode circuit means coupled to said first control store output register for decoding signals corresponding to said control sequence code; and, hardware control sequencing means coupled to said sequence decode circuit means for generating sequences of control signals for defining the operations to be performed during selected ones of said phases of instruction processing; said first control store being conditioned in response to said signals corresponding to each operation code of an instruction stored in said first register to read out the contents of a predetermined one of said plurality locations into said first control store output register and said decode circuit means in response to said control sequence code condtioning said hardware control sequencing means for generating a predetermined sequence of said control signals for enabling the completion of the operations of as many of said selected ones of said different successive phases under hardwired control before transferring control to said one microinstruction of one of said execution sequences of said second control store specified by said address read out from said predetermined location of said first addressable store.

Claim 38

The system of claim 34 wherein said hardware control sequence means further includes: instruction cycle control means connected to said decode circuit means for generating signals corresponding to sequences of control states defining the sequences of operations to be performed by said processing unit during said first one of said phases; and, hardware logic decode circuit means coupled to said instruction cycle control means and to said first control store output register, said cycle control means being conditioned by said decode circuit means to generate signals corresponding to a first predetermined one of said sequences of control states for conditioning said hardware logic decode circuit means to generate said control signals during said hardwired cycles of operation defined by the control states of said first predetermined one of said sequences.

Claim 39

The system of claim 35 wherein said hardware logic decode circuit means includes circuits for generating signals for causing a next instruction to be fetched from said cache unit apparatus and loaded into said first one of said plurality of registers.

Claim 40

The system of claim 35 wherein certain ones of said instructions have a single word format including an address which can be coded to specify that certain types of indirect address modifications be performed upon the address included therein, said cycle control means being conditioned by said control sequence decode circuit means and signals from said instruction address to generate signals corresponding to a second predetermined one of said sequences of control states for conditioning said hardware logic decode circuit means to generate control signals for conditioning said processing apparatus to perform the specified indirect address modification under hardwired control in response to said control signals.

Claim 41

The system of claim 37 wherein said those operations include operations required when any one of said addresses is coded to specify an indirect operand address.

Claim 42

The system of claim 38 wherein each instruction includes at least one address, said different successive phases of processing including an instruction cycle (I cycle) wherein instruction operand addresses are generated, a cache cycle (C cycle) wherein said cache unit fetches an operand specified by said instruction address and an execution cycle (E cycle) wherein the manipulations specified by the instruction operation code to be performed upon said operand are executed by said processing unit and wherein said first one of said phases corresponds to said I cycle.

Claim 43

The system of claim 39 wherein said hardware logic decode circuit means includes cache command decode circuit means, said cache command decode circuit means being conditioned by said control sequence code and said signals from said cycle control means to generate coded cache command signals for forwarding to said cache unit for fetching said operand specified by said instruction address as required for the execution of said instruction during said C cycle phase of operation.