US4736119A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic CMOS current surge control
Assignee: Nokia Bell Labs
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Filing: 1987-02-04
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Granted: 1988-04-05
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Expires: 2007-02-04
Abstract
Abstract Integrated circuits having a large number of transmission gate logic stages have been found to draw a large current surge on power-up. This is due to the floating input node of complementary inverters causing current to flow briefly before clock pulses arrive. The present invention provides a DC voltage on the gates of the pass transistors until the system clock pulses arrive, thereby eliminating the floating node. An optional periodic window may be generated to examine the system clock after power-up, to detect a loss of clock condition.
Inventors
- 👤 Che-Tsung Chen
- 👤 Kevin D. Kolwicz
- 👤 Chin-Jen Lin
- 👤 Won J. Yoon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:22
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/30; H; H03; H03K; H03K19/00; H03K19/0008
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
101 words
An integrated circuit comprising transmission gate logic circuitry, means for receiving a system clock signal from a system clock, and means for providing multi-phase clock signals to the gates of pass transistors connected to complementary inverters in said logic circuitry, characterized in that said integrated circuit further comprises control circuitry that causes DC voltages to be applied to said gates so as to cause said pass transistors to conduct when the power supply voltage is applied to said integrated circuit, and to thereafter cause said multi-phase clock signals to be applied to said gates when said system clock signal is detected.
Claim 2
Dependent Claim
101 words
An integrated circuit comprising transmission gate logic circuitry, means for receiving a system clock signal from a system clock, and means for providing multi-phase clock signals to the gates of pass transistors connected to complementary inverters in said logic circuitry, characterized in that said integrated circuit further comprises control circuitry that causes DC voltages to be applied to said gates so as to cause said pass transistors to conduct when the power supply voltage is applied to said integrated circuit, and to thereafter cause said multi-phase clock signals to be applied to said gates when said system clock signal is detected.
Claim 3
Dependent Claim
85 words
The integrated circuit of claim 1 wherein said control circuitry further comprises means to periodically examine said system clock during window periods after said power supply voltage is applied, and to cause DC voltages to be applied to said gates so as to cause said pass transistors to conduct if said system clock signal is not detected during a window period, and to cause said multi-phase clock signals to be applied to said gates if said system clock signal is detected during a window period.
Claim 4
Dependent Claim
47 words
The integrated circuit of claim 2 wherein said control circuitry comprises a ring oscillator for generating a window signal having a period longer than the period of said system clock signal, and a loss-of-clock detector for determining whether said system clock signal is present during the window.
Claim 5
Dependent Claim
28 words
The integrated circuit of claim 1 wherein said control circuitry comprises means for counting a multiplicity of system clock transitions in order to detect said system clock signal.
Claim 6
Dependent Claim
22 words
The integrated circuit of claim 1 wherein the means for providing multi-phase clock signals generates at least non-overlapping master and slave signals.
Claim 7
Dependent Claim
15 words
The integrated circuit of claim 1 wherein said integrated circuit is implemented in CMOS technology.
Claim 8
Dependent Claim
17 words
The integrated circuit of claim 1 wherein said system clock is located externally to said integrated circuit.
Claim 9
Dependent Claim
11 words
The integrated circuit of claim 1 further comprising said system clock.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-05 | 1991-10-05 | 1992-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-05 | 1995-10-05 | 1996-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-05 | 1999-10-05 | 2000-04-05 | $7700.00 | Window Closed / Lapsed |