US4641044A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock generator with reset and initialization circuitry
Assignee: Toshiba Corp
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Filing: 1984-11-29
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Granted: 1987-02-03
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Expires: 2004-11-29
Abstract
Abstract After detecting a leading edge of a stop control signal supplied from an external circuit, an oscillation output signal is cut off at an input side of a frequency divider in synchronism with the first leading edge of a clock signal generated from the frequency divider, thereby stopping the generation of clock signals. The stopping of the clock signal generating operation is released in such a manner that, immediately after a trailing edge of an external control signal is detected, an internal state of the frequency divider is initialized, and the oscillation output signal which has been cut off is supplied to the frequency divider again, thereby generating a proper clock signal.
Inventors
- 👤 Hajime Shiraishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 05:32
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
281 words
A clock generator receiving a pulse signal having a predetermined period comprising: frequency-dividing means for generating a clock signal by frequency dividing said pulse signal, said frequency-dividing means including a divider clear terminal for receiving a clear signal to set said frequency-dividing means into an initial state; a control terminal for receiving a control signal to stop said frequency-dividing means from generating said clock signals; first memory means, having an input terminal coupled to said control terminal, for storing a level of said control signal received at said control terminal and for providing a first memory output signal, said first memory means also having a first memory clear terminal for receiving said clear signal to set said first memory into an initial state; second memory means, coupled to said first memory means, for storing said first memory output signal of said first memory means in synchronism with the clock signal generated from said frequency-dividing means and for producing a second memory output signal, said second memory means also having a second memory clear terminal for receiving said clear signal to set said second memory means into an initial state; controlling means, coupled to receive said pulse signal and said second memory output signal, for supplying said pulse signal to said frequency-dividing means according to the state of said second memory output signal of said second memory means; and third memory means, having an input terminal coupled to said control terminal, for storing a level of said control signal supplied to said control terminal for restarting the frequency-dividing means in response to said control signal, and for supplying said clear signal to said first and second memory means and said frequency-dividing means.
Claim 2
Dependent Claim
281 words
A clock generator receiving a pulse signal having a predetermined period comprising: frequency-dividing means for generating a clock signal by frequency dividing said pulse signal, said frequency-dividing means including a divider clear terminal for receiving a clear signal to set said frequency-dividing means into an initial state; a control terminal for receiving a control signal to stop said frequency-dividing means from generating said clock signals; first memory means, having an input terminal coupled to said control terminal, for storing a level of said control signal received at said control terminal and for providing a first memory output signal, said first memory means also having a first memory clear terminal for receiving said clear signal to set said first memory into an initial state; second memory means, coupled to said first memory means, for storing said first memory output signal of said first memory means in synchronism with the clock signal generated from said frequency-dividing means and for producing a second memory output signal, said second memory means also having a second memory clear terminal for receiving said clear signal to set said second memory means into an initial state; controlling means, coupled to receive said pulse signal and said second memory output signal, for supplying said pulse signal to said frequency-dividing means according to the state of said second memory output signal of said second memory means; and third memory means, having an input terminal coupled to said control terminal, for storing a level of said control signal supplied to said control terminal for restarting the frequency-dividing means in response to said control signal, and for supplying said clear signal to said first and second memory means and said frequency-dividing means.
Claim 3
Dependent Claim
40 words
A clock generator according to claim 1, wherein said third memory means includes a third memory clear terminal coupled to said frequency-dividing means to receive a reset signal whereby said third memory means is initialized according to said reset signal.
Claim 4
Dependent Claim
40 words
A clock generator according to claim 1, wherein said first memory means comprises a flip-flop coupled to receive a signal having a constant level at a data input terminal, and coupled to receive said control signal at a clock terminal.
Claim 5
Dependent Claim
50 words
A clock generator according to claim 1, wherein said second memory means comprises a flip-flop coupled to receive said clock signal generated from said frequency dividing means at a clock terminal, and coupled to receive said first memory output signal from said first memory means at a data input terminal.
Claim 6
Dependent Claim
47 words
A clock generator according to claim 1, wherein said frequency-dividing means comprises a plurality of flip-flops connected in series to frequency divide the pulse signal having the predetermined period, and a detecting gate coupled to said plurality of flip-flops for detecting states of said plurality of flip-flops.
Claim 7
Dependent Claim
40 words
A clock generator according to claim 1, wherein said third memory means comprises a flip-flop coupled to receive a signal having a constant level at a data input terminal, and coupled to receive said control signal at a clock terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-02 | 1990-08-04 | 1991-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-02 | 1994-08-04 | 1995-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-02 | 1998-08-04 | 1999-02-03 | $7700.00 | Window Closed / Lapsed |