US4329652A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for synchronization control of a plurality of inverters
Assignee: Toshiba Corp
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Filing: 1979-02-27
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Granted: 1982-05-11
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Expires: 1999-02-27
Abstract
Abstract In controlled apparatus in which the output pulses of a common reference oscillator are the reference signals of a plurality of inverters, a synchronizing signal generated once in each cycle is added to the output pulses of the common reference oscillator. A respective control apparatus provided for each inverter detects the synchronizing signal from these output pulses to which the synchronizing signal has been added, and by this means phase matching of the outputs of the inverters is effected.
Inventors
- 👤 Osamu Higa
- 👤 Nagataka Seki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:22
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/493; H02M7/505; H03; H03K; H03K17/00; H03K5/00; H03K5/15; H03K5/15013; H03K5/1506; H03K5/15093
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
136 words
An apparatus for the synchronization control of a plurality of inverters, comprising: a reference pulse oscillator; synchronizing signal generating means responsive to the output of the reference pulse oscillator for generating distinct synchronizing signals having different widths from that of the output of the reference pulse oscillator, for adding said generated synchronizing signals to the output of the reference pulse oscillator, and for supplying an output corresponding to the sum thereof; and, a plurality of gate control means responsive to the output of the synchronizing signal generator for controlling the gates of said inverters, each gate control means coupled to a respective inverter and including means for detecting the synchronizing signals from the output of said synchronizing signal generating means and means for synchronizing the gates of said inverters by means of said detected synchronizing signals.
Claim 2
Independent Claim
136 words
An apparatus for the synchronization control of a plurality of inverters, comprising: a reference pulse oscillator; synchronizing signal generating means responsive to the output of the reference pulse oscillator for generating distinct synchronizing signals having different widths from that of the output of the reference pulse oscillator, for adding said generated synchronizing signals to the output of the reference pulse oscillator, and for supplying an output corresponding to the sum thereof; and, a plurality of gate control means responsive to the output of the synchronizing signal generator for controlling the gates of said inverters, each gate control means coupled to a respective inverter and including means for detecting the synchronizing signals from the output of said synchronizing signal generating means and means for synchronizing the gates of said inverters by means of said detected synchronizing signals.
Claim 3
Independent Claim
224 words
An apparatus for the synchronization control of a plurality of inverters, comprising: a reference oscillator; synchronizing signal generating means responsive to the output of said reference oscillator for generating distinct synchronizing signals having different widths from that of the output of said reference pulse oscillator, for adding the generated synchronizing signals to the output of said reference oscillator, and for supplying an output corresponding to the sum thereof; and a plurality of gate control means responsive to the output of said synchronizing signal generator for controlling the gates of said inverters, each gate control means coupled to a respective inverter, and comprising a synchronizing signal detector for detecting synchronizing signals from the output of said synchronizing signal generating means, and a ring counter responsive to the output of said synchronizing signal generating means and controlled by the output of said synchronizing signal detector signal means wherein each of said gate control means includes a synchronizing signal detector, and an AND logic gate having one input terminal connected to the output terminal of said synchronizing signal detector and another input terminal for receiving run command signals, a flip-flop having a set terminal connected to the output terminal of said AND logic gate, said flip-flop having a reset terminal for receiving stop command signals, and a monostable multivibrator connected to the output terminal of said flip-flop.
Claim 4
Independent Claim
224 words
An apparatus for the synchronization control of a plurality of inverters, comprising: a reference oscillator; synchronizing signal generating means responsive to the output of said reference oscillator for generating distinct synchronizing signals having different widths from that of the output of said reference pulse oscillator, for adding the generated synchronizing signals to the output of said reference oscillator, and for supplying an output corresponding to the sum thereof; and a plurality of gate control means responsive to the output of said synchronizing signal generator for controlling the gates of said inverters, each gate control means coupled to a respective inverter, and comprising a synchronizing signal detector for detecting synchronizing signals from the output of said synchronizing signal generating means, and a ring counter responsive to the output of said synchronizing signal generating means and controlled by the output of said synchronizing signal detector signal means wherein each of said gate control means includes a synchronizing signal detector, and an AND logic gate having one input terminal connected to the output terminal of said synchronizing signal detector and another input terminal for receiving run command signals, a flip-flop having a set terminal connected to the output terminal of said AND logic gate, said flip-flop having a reset terminal for receiving stop command signals, and a monostable multivibrator connected to the output terminal of said flip-flop.
References Cited (Backward Citations)
US3586884A
Cited
US3581213A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-05-10 | 1985-11-09 | 1986-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-05-10 | 1989-11-09 | 1990-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-05-10 | 1993-11-09 | 1994-05-11 | $7700.00 | Window Closed / Lapsed |