Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same

Claim 1

A method for fabricating a thermally-enhanced stacked-die BGA semiconductor package, comprising the steps of: (1) preparing a substrate having a front surface and a back surface; (2) mounting a first semiconductor chip having an active surface and an inactive surface over the substrate, wherein the active surface of the first semiconductor chip is bonded and electrically coupled to the front surface of the substrate through flip-chip technology; (3) mounting a heat spreader over the first semiconductor chip, the heat spreader having a support portion and an overhead portion formed with a plurality of wire-routing openings, the heat spreader being mounted in such a manner that the support portion is supported on the front surface of the substrate, while the overhead portion is abutted on the inactive surface of the first semiconductor chip; (4) mounting a second semiconductor chip having an active surface and an inactive surface over the overhead portion of the heat spreader, wherein the inactive surface of the second semiconductor chip is thermally coupled to the overhead portion of the heat spreader; (5) providing a plurality of bonding wires for electrically coupling the second semiconductor chip to the substrate, wherein the bonding wires are routed from the active surface of the second semiconductor chip through die wire-routing openings in the overhead portion of the heat spreader down to the front surface of the substrate; (6) performing an encapsulation process to form an encapsulation body for encapsulating the front surface of the substrate, the first semiconductor chip, the heat spreader, the second semiconductor chip, and the bonding wires; and (7) performing a ball-implantation process to implant an array of solder balls over the back surface of the substrate.

Claim 2

A method for fabricating a thermally-enhanced stacked-die BGA semiconductor package, comprising the steps of: (1) preparing a substrate having a front surface and a back surface; (2) mounting a first semiconductor chip having an active surface and an inactive surface over the substrate, wherein the active surface of the first semiconductor chip is bonded and electrically coupled to the front surface of the substrate through flip-chip technology; (3) mounting a heat spreader over the first semiconductor chip, the heat spreader having a support portion and an overhead portion formed with a plurality of wire-routing openings, the heat spreader being mounted in such a manner that the support portion is supported on the front surface of the substrate, while the overhead portion is abutted on the inactive surface of the first semiconductor chip; (4) mounting a second semiconductor chip having an active surface and an inactive surface over the overhead portion of the heat spreader, wherein the inactive surface of the second semiconductor chip is thermally coupled to the overhead portion of the heat spreader; (5) providing a plurality of bonding wires for electrically coupling the second semiconductor chip to the substrate, wherein the bonding wires are routed from the active surface of the second semiconductor chip through die wire-routing openings in the overhead portion of the heat spreader down to the front surface of the substrate; (6) performing an encapsulation process to form an encapsulation body for encapsulating the front surface of the substrate, the first semiconductor chip, the heat spreader, the second semiconductor chip, and the bonding wires; and (7) performing a ball-implantation process to implant an array of solder balls over the back surface of the substrate.