US6501164B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-chip semiconductor package with heat dissipating structure
Assignee: Siliconware Precision Industries Co Ltd
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Filing: 2001-12-20
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Granted: 2002-12-31
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Expires: 2021-12-20
Abstract
Abstract A multi-chip semiconductor package with a heat dissipating structure is proposed, in which a chip receiving cavity and an opening respectively formed in the heat dissipating structure and a chip carrier, are used to accommodate semiconductor chips therein with the chips being in direct contact with the heat dissipating structure, allowing heat generated by the chips to be rapidly dissipated through the heat dissipating structure. With the provision of through holes for interconnecting the chip receiving cavity and opening, gold wires pass the through holes and electrically connect the chips to the chip carrier. Such a structure with chips embedded in the chip receiving cavity and opening makes internal elements to be more compactly arranged in the semiconductor package, which is preferable in response to profile miniaturization of electronic product development.
Inventors
- 👤 Ying-Chieh Chen
- 👤 Jeng-Yuan Lai
- 👤 Jzu-Yi Tien
- 👤 Chiung-Kai Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 16:40
CPC Classifications
H; H10; H10W; H10W40/00; H10W40/10; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W74/117; H10W90/00; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/681; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W72/29; H10W72/30; H10W72/381; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/851; H10W72/853; H10W72/865; H10W72/874; H10W72/884; H10W72/90; H10W72/941; H10W72/944; H10W72/9445; H10W74/131; H10W74/142; H10W90/20; H10W90/22; H10W90/231; H10W90/288; H10W90/291; H10W90/701; H10W90/731; H10W90/732; H10W90/734; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
176 words
A multi-chip semiconductor package with a heat dissipating structure, comprising: a chip carrier having at least one opening thereon; a heat dissipating structure attached onto the chip carrier for covering the opening of the chip carrier, wherein the heat dissipating structure is formed with an outwardly-opened cavity corresponding in position above the opening of the chip carrier, and a plurality of through portions for interconnecting the cavity and the opening of the chip carrier; at least one first chip having an active surface and an opposing non-active surface, and received in the cavity with the active surface thereof being attached to the cavity; at least one second chip having an active surface and an opposing non-active surface, and received in the opening of the chip carrier with the non-active surface thereof being attached to the heat dissipating structure; a plurality of conductive elements passing through the through portions, for electrically connecting at least one of the chips to the chip carrier; and an encapsulant for encapsulating the first chip, the second chip and the conductive elements.
Claim 2
Dependent Claim
176 words
A multi-chip semiconductor package with a heat dissipating structure, comprising: a chip carrier having at least one opening thereon; a heat dissipating structure attached onto the chip carrier for covering the opening of the chip carrier, wherein the heat dissipating structure is formed with an outwardly-opened cavity corresponding in position above the opening of the chip carrier, and a plurality of through portions for interconnecting the cavity and the opening of the chip carrier; at least one first chip having an active surface and an opposing non-active surface, and received in the cavity with the active surface thereof being attached to the cavity; at least one second chip having an active surface and an opposing non-active surface, and received in the opening of the chip carrier with the non-active surface thereof being attached to the heat dissipating structure; a plurality of conductive elements passing through the through portions, for electrically connecting at least one of the chips to the chip carrier; and an encapsulant for encapsulating the first chip, the second chip and the conductive elements.
Claim 3
Dependent Claim
21 words
The multi-chip semiconductor package of claim 1 , wherein the semiconductor package is a cavity down BGA (ball grid array) package.
Claim 4
Dependent Claim
36 words
The multi-chip semiconductor package of claim 1 , wherein the chip carrier is a substrate made of a material selected from a group consisting of BT (bismaleimide-triazine) resin, epoxy resin, polyimide resin, triazine resin and ceramics.
Claim 5
Dependent Claim
19 words
The multi-chip semiconductor package of claim 1 , wherein the chip carrier is a TAB (tape automated bonding) tape.
Claim 6
Dependent Claim
23 words
The multi-chip semiconductor package of claim 1 , wherein the opening of the chip carrier is used for receiving the second chip therein.
Claim 7
Dependent Claim
22 words
The multi-chip semiconductor package of claim 1 , wherein the cavity is a chip receiving cavity for receiving the first chip therein.
Claim 8
Dependent Claim
23 words
The multi-chip semiconductor package of claim 1 , wherein the non-active surface of the first chip is exposed to outside of the encapsulant.
Claim 9
Dependent Claim
18 words
The multi-chip semiconductor package of claim 1 , wherein the first chip is completely embedded in the cavity.
Claim 10
Dependent Claim
15 words
The multi-chip semiconductor package of claim 1 , wherein the through portions are through holes.
Claim 11
Dependent Claim
35 words
The multi-chip semiconductor package of claim 1 , wherein the active surface of the first chip is formed with a plurality of bonding pads thereon, and the bonding pads are exposed to the through portions.
Claim 12
Dependent Claim
37 words
The multi-chip semiconductor package of claim 1 , wherein the conductive elements are gold wires. 12 .The multi-chip semiconductor package of claim 1 , wherein the heat dissipating structure is mounted with an external heat sink thereon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-12-30 | 2006-07-01 | 2006-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-12-30 | 2010-07-01 | 2010-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-12-30 | 2014-07-01 | 2014-12-31 | $7700.00 | Window Closed / Lapsed |