Patent US2138706A successfully refreshed from Google Patents.
Patent US6653700B2 successfully refreshed from Google Patents.
US6653700B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor structure and method of fabrication
Assignee: Intel Corp
•
Filing: 2002-07-08
•
Granted: 2003-11-25
•
Expires: 2022-07-08
Abstract
Abstract A novel transistor structure and its method of fabrication. According to the present invention, the transistor includes an intrinsic silicon body having a first surface. A gate dielectric is formed on the first surface of the intrinsic silicon body. A gate electrode is formed on the gate dielectric wherein the gate electrode comprises a mid-gap work function film on the gate dielectric. A pair of source/drain regions are formed on opposite sides of the intrinsic silicon body.
Inventors
- 👤 Robert S. Chau
- 👤 Jack Kavalieros
- 👤 Anand Murthy
- 👤 Brian Roberds
- 👤 Brian S. Doyle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:01
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6739; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D30/0212; H10D30/027; H10D30/0275; H10D64/60; H10D64/66; H10D64/665; H10D64/667; H10D64/668; Y; Y10; Y10S; Y10S977/00; Y10S977/70; Y10S977/701; Y10S977/72; Y10S977/721; Y10S977/902; Y10S977/932; Y10S977/936
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
100 words
A method of forming a transistor comprising: forming an intrinsic silicon film having a first surface on an insulating substrate; forming a gate dielectric layer on said first surface of said intrinsic silicon body; forming a gate electrode on said gate dielectric, wherein said gate electrode comprises a mid-gap work function film having a thickness of less than or equal to 100 Å on said gate dielectric; forming a doped polysilicon film having a thickness of around 1000 Å on said mid-gap work function film; and forming a pair of source/drain regions on opposite sides of said intrinsic silicon body.
Claim 2
Independent Claim
100 words
A method of forming a transistor comprising: forming an intrinsic silicon film having a first surface on an insulating substrate; forming a gate dielectric layer on said first surface of said intrinsic silicon body; forming a gate electrode on said gate dielectric, wherein said gate electrode comprises a mid-gap work function film having a thickness of less than or equal to 100 Å on said gate dielectric; forming a doped polysilicon film having a thickness of around 1000 Å on said mid-gap work function film; and forming a pair of source/drain regions on opposite sides of said intrinsic silicon body.
Claim 3
Dependent Claim
31 words
The method of claim 1 further comprising forming a silicon or silicon alloy film on said first surface of said intrinsic silicon film adjacent to and separated from said gate electrode.
Claim 4
Dependent Claim
20 words
The method of claim 2 wherein said silicon or silicon alloy film is an epitaxial silicon or silicon alloy film.
Claim 5
Dependent Claim
20 words
The method of claim 1 wherein said intrinsic silicon body is formed to a thickness of less than 500 Å.
Claim 6
Dependent Claim
18 words
The method of claim 4 wherein said thickness of said intrinsic silicon body is less than 100 Å.
Claim 7
Dependent Claim
33 words
The method of claim 1 wherein said insulating substrate is selected from the group consisting of silicon dioxide on silicon, diamond, sapphire, non conducting polymers, quartz, gallium arsinide, and wide band gap semiconductors.
Claim 8
Dependent Claim
21 words
The method of claim 1 wherein said mid-gap work function film has a work function between 4.65 eV to 4.9 eV.
Claim 9
Dependent Claim
27 words
The method of claim 1 wherein said mid-gap work function film is selected from the group consisting of titanium nitride, tungsten, titanium, molybdenum, tantalum, and metallic silicides.
References Cited (Backward Citations)
US5293053A
Cited
US5164805A
Cited
US5079180A
Cited
US5279978A
Cited
US5362660A
Cited
US5783478A
Cited
US5643817A
Cited
US5663570A
Cited
US5434093A
Cited
US5583368A
Cited
US5627097A
Cited
US5714413A
Cited
US6424016B1
Cited
US5998289A
Cited
US6239472B1
Cited
US6254676B1
Cited
US20020119615A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-11-24 | 2007-05-26 | 2007-11-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-11-24 | 2011-05-26 | 2011-11-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-11-24 | 2015-05-26 | 2015-11-25 | $7700.00 | Window Closed / Lapsed |