Elevated CMOS

Claim 2

An integrated circuit device comprising: a dielectric layer having a recess therein; an n-type insulated gate vertical-channel field effect transistor having its vertical-channel within, and on one side of said recess; a p-type insulated gate vertical-channel field effect transistor having its vertical-channel within, and on another side of said recess opposite from the vertical-channel of said n-type insulated gate vertical-channel field effect transistor; and a control gate disposed in said recess between said n-type and p-type insulated gate vertical-channel field effect transistors connected to control current flow in said vertical-channel of both said n-type and said p-type insulated gate vertical-channel field effect transistors.

Claim 3

The device of claim 1, wherein said recess has substantially vertical sidewalls.

Claim 4

The device of claim 1 wherein said dielectric comprises an oxide of silicon.

Claim 5

The device of claim 1, wherein said control gate is part of a thin film layer which has a constant thickness which is at least 20% to 50% of the minimum width of said recess.

Claim 6

The device of claim 1, wherein said control gate is separated from said respective vertical-channel regions of said n-type and p-type insulated gate vertical-channel field effect transistors by a gate dielectric having a dielectric thickness less than, 500 A of silicon dioxide.

Claim 7

The device of claim 1 further comprising a plurality of other recesses in said dielectric layer containing respective n-channel transistors, wherein some of said respective a n-channel transistors have width-to-length ratios (W/L) significantly different from the width-to-length ratios of others of said respective n-channel transistors.

Claim 8

An integrated circuit device comprising: a dielectric layer including therein a recess with substantially vertical sidewalls; a first insulated gate field effect transistor disposed within and adjacent to a first sidewall of said recess, said first insulated gate field effect transistor having a first source/drain and a second source/drain separated from one another vertically along said first sidewall of said recess by a channel region and a second insulated gate field effect transistor disposed within and adjacent to a second sidewall of said recess, said second insulated gate field effect transistor having a first source/drain and a second source/drain separated from one another vertically along said second sidewall of said recess by a channel region, wherein said first and second insulated gate field effect transistors are of complementary conductivity types; and a control gate disposed within said recess between the channel regions of said first and second insulated gate field effect transistors to control current flow in both said first and second transistors.

Claim 9

An integrated circuit device comprising: a dielectric layer including therein a recess with substantially vertical sidewalls; a first insulated gate field effect transistor disposed within and adjacent to a first sidewall of said recess, said first insulated gate field effect transistor having a first source/drain and a second source/drain separated from one another vertically along said first sidewall of said recess by a channel region and a second insulated gate field effect transistor disposed within and adjacent to a second sidewall of said recess, said second insulated gate field effect transistor having a first source/drain and a second source/drain separated from one another vertically along said second sidewall of said recess by a channel region, wherein said first and second insulated gate field effect transistors are of complementary conductivity types; and a control gate disposed within said recess between the channel regions of said first and second insulated gate field effect transistors to control current flow in both said first and second transistors.

Claim 10

The device of claim 7, wherein said control gate is part of a thin film layer which has a constant thickness which is at least 20% to 50% of the minimum width of said recess.

Claim 11

The device of claim 7, wherein said channel region of each of said first and second insulated gate field effect transistors is essentially monocrystalline.

Claim 12

The device of claim 7, wherein said control gate is capacitively coupled to said channel regions through gate dielectrics each having a dielectric thickness less than 500 A of silicon dioxide.

Claim 13

The device of claim 10, wherein each of said gate dielectrics is less than 300 Angstroms thick and consists essentially of silicon dioxide.

Claim 14

The device of claim 7, wherein said control gate contains more than 30% silicon by atomic weight and is not monocrystalline.

Claim 15

The device of claim 7, wherein said dielectric layer has a thickness in the ranger of 6000 A-15000 A inclusive.

Claim 16

The device of claim 7, wherein said first and second insulated gate field effect transistors each have a minimum thickness, between said control gate and one of said first and second sidewall of said dielectric layer, in the range of 1000 A-8000 A inclusive.

Claim 17

The device of claim 7, further comprising a plurality of other recesses in said dielectric layer , at least one of which contains only a single transistor.

Claim 18

The device of claim 7, wherein said second source/drains of both said first and second insulated gate field effect transistors are ohmically contacted at a contact hole within said recess.