US6621312B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
High bandwidth multi-phase clock selector with continuous phase output
Assignee: Infineon Technologies Austria AG
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Filing: 2001-11-13
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Granted: 2003-09-16
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Expires: 2021-11-13
Abstract
Abstract The present invention includes a system and method for improving phase selection using a phase selector system. An exemplary phase selector system of the present invention includes a high speed phase selector having control logic, XOR gates, and a selector. The control logic uses Gray coding to generate one or more control signals. For example, the control logic uses a 3 bit word to select a phase for clock recovery. A selector coupled to the control logic determines the phase selected. XOR gates coupled between the control logic and the selector provide eight phases of a clock using four input phases of the clock with inversion. In this manner, a four to one selector can choose one of eight phases from the XOR gates to aid in clock recovery. The selector control logic has a continuous output phase during a change to an adjacent phase, which substantially prevents glitching on the clock.
Inventors
- 👤 Benjamin Tang
- 👤 Keith Bassett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:54
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0995; H03L7/0996; H03L7/07; H03L7/081; H03L7/0812; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
84 words
A high speed phase selector system, comprising: control logic using Gray coding for generating at least one control signal for phase selection; a selector having multiple inputs coupled to the control logic, wherein the multiple inputs correspond to multiple phases of a high frequency periodic waveform clock for determining the phase selected, and a plurality of XOR gates coupled between the control logic and the multiple inputs of the selector for providing additional phases to the selector using logic inversion of the multiple inputs.
Claim 2
Dependent Claim
84 words
A high speed phase selector system, comprising: control logic using Gray coding for generating at least one control signal for phase selection; a selector having multiple inputs coupled to the control logic, wherein the multiple inputs correspond to multiple phases of a high frequency periodic waveform clock for determining the phase selected, and a plurality of XOR gates coupled between the control logic and the multiple inputs of the selector for providing additional phases to the selector using logic inversion of the multiple inputs.
Claim 3
Dependent Claim
27 words
The high speed phase selector system of claim 1 , wherein the selector determines the phase selected by aligning the clock with data used in clock recovery.
Claim 4
Dependent Claim
67 words
A high speed phase selector system, comprising: control logic using Gray coding to generate a control signal consisting of a binary word; a selector coupled to the control logic for receiving the control signal to determine the phase selected, and four XOR gates coupled between the control logic and the selector for providing eight phases of a clock using four input phases of the clock with inversion.
Claim 5
Dependent Claim
67 words
A high speed phase selector system, comprising: control logic using Gray coding to generate a control signal consisting of a binary word; a selector coupled to the control logic for receiving the control signal to determine the phase selected, and four XOR gates coupled between the control logic and the selector for providing eight phases of a clock using four input phases of the clock with inversion.
Claim 6
Dependent Claim
27 words
The phase selector system of claim 3 , wherein one XOR gate is turned on indicating the selected phase and the remaining XOR gates are turned off.
Claim 7
Dependent Claim
54 words
A phase selector system, comprising: four XOR gates having four input phases where each XOR gate is configured to output one of two input phases using inversion; and a four to one selector coupled to the outputs of the four XOR gates for selecting a phase from the outputs of the four XOR gates.
Claim 8
Dependent Claim
54 words
A phase selector system, comprising: four XOR gates having four input phases where each XOR gate is configured to output one of two input phases using inversion; and a four to one selector coupled to the outputs of the four XOR gates for selecting a phase from the outputs of the four XOR gates.
Claim 9
Dependent Claim
99 words
A phase selector system, comprising: control logic for selecting a phase; first, second, third, and fourth XOR gates having the control logic coupled to the inputs of the first, second, third, and fourth XOR gates, wherein the control logic selects a phase and inputs the selected phase to the inputs of the first, second, third, and fourth XOR gates; and a four to one selector coupled to the outputs of the first, second, third, and fourth XOR gates for receiving the selected phase from at least one of the outputs of the first, second, third, and fourth XOR gates.
Claim 10
Dependent Claim
99 words
A phase selector system, comprising: control logic for selecting a phase; first, second, third, and fourth XOR gates having the control logic coupled to the inputs of the first, second, third, and fourth XOR gates, wherein the control logic selects a phase and inputs the selected phase to the inputs of the first, second, third, and fourth XOR gates; and a four to one selector coupled to the outputs of the first, second, third, and fourth XOR gates for receiving the selected phase from at least one of the outputs of the first, second, third, and fourth XOR gates.
Claim 11
Dependent Claim
35 words
The phase selector system of claim 6 , wherein the control logic uses Gray coding and is coupled to the inputs of the first, second, third, and fourth XOR gates via one or more transistors.
Claim 12
Dependent Claim
41 words
The phase selector system of claim 6 , wherein the four to one selector includes a differential pair of transistors coupled between each output of the first, second, third, and fourth XOR gates and the output of the phase selector system.
Claim 13
Dependent Claim
68 words
The phase selector system of claim 6 , wherein: the control logic uses Gray coding and is coupled to the inputs of the first, second, third, and fourth XOR gates via one or more transistors; and the four to one selector includes a differential pair of transistors coupled between each output of the first, second, third, and fourth XOR gates and the output of the phase selector system.
Claim 14
Dependent Claim
80 words
A phase selector, comprising: control logic for generating at least one control signal and configuring multiple sets of control logic, wherein each set includes control words delayed by a fixed amount; and a selector coupled to the control logic for receiving the at least one control signal to determine the phase selected, wherein the control logic provides a portion of the enabling current to the selector such that the switching of the selected phase occurs in a substantially smooth manner.
Claim 15
Dependent Claim
80 words
A phase selector, comprising: control logic for generating at least one control signal and configuring multiple sets of control logic, wherein each set includes control words delayed by a fixed amount; and a selector coupled to the control logic for receiving the at least one control signal to determine the phase selected, wherein the control logic provides a portion of the enabling current to the selector such that the switching of the selected phase occurs in a substantially smooth manner.
Claim 16
Dependent Claim
87 words
A clock recovery system used in delay locked loops, comprising: a high speed phase selector including control logic using Gray coding to generate at least one control signal and a selector coupled to the control logic for receiving the at least one control signal to determine the phase selected; a phase detector coupled to the high speed phase selector for detecting the phase selected; and an integrator coupled to the high speed phase selector and the phase detector for receiving the phase detected and performing clock recovery.
Claim 17
Dependent Claim
87 words
A clock recovery system used in delay locked loops, comprising: a high speed phase selector including control logic using Gray coding to generate at least one control signal and a selector coupled to the control logic for receiving the at least one control signal to determine the phase selected; a phase detector coupled to the high speed phase selector for detecting the phase selected; and an integrator coupled to the high speed phase selector and the phase detector for receiving the phase detected and performing clock recovery.
Claim 18
Independent Claim
89 words
A method for selecting a phase in a delay locked loop, comprising the steps of: configuring control logic to use Gray coding to select one or more phases; generating eight phases of a clock using four input phases of the clock with XOR inversion, configuring the phase selector for receiving the selected phase from the control logic in order to perform clock recovery, and determining the selected phase via the delay locked loop coupled to the control logic in order to select the output phase of a phase selector.
Claim 19
Independent Claim
89 words
A method for selecting a phase in a delay locked loop, comprising the steps of: configuring control logic to use Gray coding to select one or more phases; generating eight phases of a clock using four input phases of the clock with XOR inversion, configuring the phase selector for receiving the selected phase from the control logic in order to perform clock recovery, and determining the selected phase via the delay locked loop coupled to the control logic in order to select the output phase of a phase selector.
Claim 20
Dependent Claim
49 words
The method of claim 12 , further comprising the steps of: receiving at least one control signal from the control logic to determine the phase selected for clock recovery; and using the control signal to generate the selected phase for the phase selector in order to perform clock recovery.
Claim 21
Dependent Claim
66 words
The method of claim 12 , further comprising the steps of: using first, second, third, and fourth XOR gates for receiving the selected phase from the control logic and outputting the selected phase to the phase selector; and configuring the phase selector for receiving the selected phase from at least one of the first, second, third, and fourth XOR gates in order to perform clock recovery.
Claim 22
Independent Claim
97 words
A method for selecting the phase in a phase selector system, comprising the steps of: configuring multiple sets of control logic, wherein each set includes control words delayed by a fixed amount to select one or more phases; generating eight phases of a clock using the multiple sets of control logic and four input phases of the clock with inversion; selecting the phase via a phase selector coupled to the control logic, and providing a portion of the enabling current to the selector such that the switching of the selected phase occurs in a substantially smooth manner.
Claim 23
Independent Claim
97 words
A method for selecting the phase in a phase selector system, comprising the steps of: configuring multiple sets of control logic, wherein each set includes control words delayed by a fixed amount to select one or more phases; generating eight phases of a clock using the multiple sets of control logic and four input phases of the clock with inversion; selecting the phase via a phase selector coupled to the control logic, and providing a portion of the enabling current to the selector such that the switching of the selected phase occurs in a substantially smooth manner.
Claim 24
Dependent Claim
66 words
The method of claim 15 , further comprising the steps of: using first, second, third, and fourth XOR gates for receiving the selected phase from the control logic and outputting the selected phase to the phase selector; and configuring the phase selector for receiving the selected phase from at least one of the first, second, third, and fourth XOR gates in order to perform clock recovery.
Claim 25
Dependent Claim
24 words
The method of claim 16 , further comprising the step of configuring control logic to use Gray coding to select one or more phases.
Claim 26
Independent Claim
24 words
The method of claim, 15 , further comprising the step of configuring control logic to use Gray coding to select one or more phases.
Claim 27
Dependent Claim
20 words
The method of claim 15 , wherein a portion of the enabling current is about one-half of the enabling current.
Claim 28
Dependent Claim
114 words
A phase selector, comprising: control logic for generating at least one control signal and configuring multiple sets of control logic, wherein each set includes control words delayed by a fixed amount; a selector having multiple inputs coupled to the control logic for receiving the at least one control signal to determine the phase selected, and a plurality of XOR gates coupled between the control logic and the multiple inputs of the selector for providing additional phases to the selector using logic inversion of the multiple inputs, wherein the control logic provides a portion of the enabling current to the selector such that the switching of the selected phase occurs in a substantially smooth manner.
Claim 29
Dependent Claim
114 words
A phase selector, comprising: control logic for generating at least one control signal and configuring multiple sets of control logic, wherein each set includes control words delayed by a fixed amount; a selector having multiple inputs coupled to the control logic for receiving the at least one control signal to determine the phase selected, and a plurality of XOR gates coupled between the control logic and the multiple inputs of the selector for providing additional phases to the selector using logic inversion of the multiple inputs, wherein the control logic provides a portion of the enabling current to the selector such that the switching of the selected phase occurs in a substantially smooth manner.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-09-15 | 2007-03-17 | 2007-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-09-15 | 2011-03-17 | 2011-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-09-15 | 2015-03-17 | 2015-09-16 | $7700.00 | Window Closed / Lapsed |