US5561692A
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Clock phase shifting method and apparatus
Assignee: Nortel Networks Ltd
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Filing: 1993-12-09
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Granted: 1996-10-01
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Expires: 2013-12-09
Abstract
Abstract A circuit for providing a phase controlled clock output includes a ring oscillator having a delay line for providing an internal clock signal whose period varies with on-chip variations due to temperature, voltage, and process. The circuit also includes a clock phase select circuit having a counter and divider for determining the number of delays in one external clock period and an input for a phase select value. A delay line having delay elements similar to those of the ring oscillator provides multiple delayed clock signals from the reference clock signal. A multiplexor having odd and even sides is used to select the desired clock signal in a glitchless manner. The phase controlled clock signal output is controlled by the phase select signal and is compensated for on-chip variations due to temperature, voltage, and process.
Inventors
- 👤 Roger J. Maitland
- 👤 Hal H. Ireland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 08:45
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/135; H03K5/131
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
311 words
A method of providing a phase controlled clock signal, in an integrated circuit comprising the steps of: providing an on-chip ring oscillator comprised of a plurality of predetermined gates for providing an internal reference clock signal having a clock signal period T osc , the delay through each of the predetermined gates being dependent upon temperature, process, and voltage variations; providing an external reference clock signal generated off-chip having a period T ref , T ref being shorter than that of internal reference clock signal period, T osc ; determining the number of external reference clock signal periods T ref in one internal reference clock signal period, T osc ; determining the propagation delay through one of predetermined gates of the ring oscillator, the propagation delay being representative of the delay through other gates of the ring oscillator; providing a phase select value indicative of a desired phase shift of the external reference clock signal; providing a delay line having a plurality of delay gates, the propagation delay through each of the delay gates being substantially the same as the propagation delay through each of the predetermined gates of the ring oscillator and being equally dependent upon temperature, process, and voltage variations; inputting the external reference clock signal info the delay line, tapping the delay line after each of the plurality of delay gates to provide a plurality of delayed external reference clock signals; determining in dependence upon the phase select value, how many delay line gates, each having the determined propagation delay, are required to delay the external reference clock signal by the desired phase shift corresponding to the phase select value; selecting a tap of the delay line which corresponds to the number of delay line gates determined in dependence upon the phase select value; and outputting the signal of the selected tap as the phase controlled clock signal.
Claim 2
Independent Claim
311 words
A method of providing a phase controlled clock signal, in an integrated circuit comprising the steps of: providing an on-chip ring oscillator comprised of a plurality of predetermined gates for providing an internal reference clock signal having a clock signal period T osc , the delay through each of the predetermined gates being dependent upon temperature, process, and voltage variations; providing an external reference clock signal generated off-chip having a period T ref , T ref being shorter than that of internal reference clock signal period, T osc ; determining the number of external reference clock signal periods T ref in one internal reference clock signal period, T osc ; determining the propagation delay through one of predetermined gates of the ring oscillator, the propagation delay being representative of the delay through other gates of the ring oscillator; providing a phase select value indicative of a desired phase shift of the external reference clock signal; providing a delay line having a plurality of delay gates, the propagation delay through each of the delay gates being substantially the same as the propagation delay through each of the predetermined gates of the ring oscillator and being equally dependent upon temperature, process, and voltage variations; inputting the external reference clock signal info the delay line, tapping the delay line after each of the plurality of delay gates to provide a plurality of delayed external reference clock signals; determining in dependence upon the phase select value, how many delay line gates, each having the determined propagation delay, are required to delay the external reference clock signal by the desired phase shift corresponding to the phase select value; selecting a tap of the delay line which corresponds to the number of delay line gates determined in dependence upon the phase select value; and outputting the signal of the selected tap as the phase controlled clock signal.
Claim 3
Dependent Claim
65 words
The method as claimed in claim 1 further including the step of subtracting a predetermined fixed number of delay line gates, equal to and representative of additional delays introduced in the step of selecting, from the number of delay line gates determined in dependence upon the phase select value, and selecting a tap of the delay line which corresponds to the resultant number of gates.
Claim 4
Dependent Claim
38 words
The method as claimed in claim 1 or claim 2 further including the step of dividing the internal clock signal by an integral value `n` to provide the internal reference clock signal having a period nT osc .
Claim 5
Dependent Claim
311 words
Apparatus for providing a phase controlled clock signal on an integrated circuit comprising: a ring oscillator comprised of a plurality of predetermined gates for providing an internal reference clock signal having a clock signal period T osc , the delay through each of the predetermined gates being dependent upon temperature, process, and voltage variations; an input for receiving an external reference clock signal having a period T ref , T ref being shorter than that of internal reference clock signal period, T osc ; means for determining the number of external reference clock signal periods T ref in one internal reference clock signal period, T osc ; means for determining the propagation delay through one of predetermined gates of the ring oscillator, the propagation delay being representative of the delay through other gates of the ring oscillator; an input for receiving a phase select value indicative of a desired phase shift of the external reference clock signal; a multitapped delay line having a plurality of delay gates and a corresponding plurality of delay line taps, the propagation delay through each of the delay gates being substantially the same as the propagation delay through each of the predetermined gates of the ring oscillator and being equally dependent upon temperature, process, and voltage variations, the delay line having its input connected to the input which receives the external reference clock signal; means for determining in dependence upon the phase select value, how many delay line gates, each having the determined propagation delay, are required to delay the external reference clock signal by the desired phase shift corresponding to the phase select value; a multiplexer for selecting and outputting a signal on a fop of the delay line which corresponds to the number of delay line gates determined in dependence upon the phase select value, wherein the signal represents the phase control clock signal.
Claim 6
Dependent Claim
311 words
Apparatus for providing a phase controlled clock signal on an integrated circuit comprising: a ring oscillator comprised of a plurality of predetermined gates for providing an internal reference clock signal having a clock signal period T osc , the delay through each of the predetermined gates being dependent upon temperature, process, and voltage variations; an input for receiving an external reference clock signal having a period T ref , T ref being shorter than that of internal reference clock signal period, T osc ; means for determining the number of external reference clock signal periods T ref in one internal reference clock signal period, T osc ; means for determining the propagation delay through one of predetermined gates of the ring oscillator, the propagation delay being representative of the delay through other gates of the ring oscillator; an input for receiving a phase select value indicative of a desired phase shift of the external reference clock signal; a multitapped delay line having a plurality of delay gates and a corresponding plurality of delay line taps, the propagation delay through each of the delay gates being substantially the same as the propagation delay through each of the predetermined gates of the ring oscillator and being equally dependent upon temperature, process, and voltage variations, the delay line having its input connected to the input which receives the external reference clock signal; means for determining in dependence upon the phase select value, how many delay line gates, each having the determined propagation delay, are required to delay the external reference clock signal by the desired phase shift corresponding to the phase select value; a multiplexer for selecting and outputting a signal on a fop of the delay line which corresponds to the number of delay line gates determined in dependence upon the phase select value, wherein the signal represents the phase control clock signal.
Claim 7
Dependent Claim
94 words
The apparatus as claimed in claim 4 wherein the means for determining, in dependence upon the phase select value, how many delay line gates are required to delay the external reference clock signal by the desired phase shift includes means for subtracting a predetermined fixed number of delay line gates, equal to and representative of additional delays introduced in the multiplexer, from the number of delay line gates determined in dependence upon the phase select value, and means for selecting a tap of the delay line which corresponds to the resultant number of gates.
Claim 8
Independent Claim
49 words
The apparatus as claimed in claims 4 or 5 wherein the multiplexor includes an odd side and an even side, the odd side connected to outputs of odd taps of the multitapped delay line and the even side connected to outputs of even taps of the multitapped delay line.
Claim 9
Dependent Claim
16 words
The apparatus as claimed in claim 6 wherein the multiplexor includes four stages on each side.
Claim 10
Dependent Claim
28 words
The apparatus as claimed in claim 7 wherein the first three stages of each side are cascaded and have an input for enabling by first respective select signal.
Claim 11
Dependent Claim
37 words
The apparatus as claimed in claim 8 wherein the fourth stage is shared by each side, is connected to the first three stages of each side and has an inputs for enabling by second respective select signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-01 | 2000-04-01 | 2000-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-01 | 2004-04-01 | 2004-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-01 | 2008-04-01 | 2008-10-01 | $7700.00 | Window Closed / Lapsed |