Digital phase locked loop clock recovery scheme

Claim 1

A clock recovery arrangement responsive to an incoming digital data stream for generating therefrom a retimed data output signal and a recovered clock output signal, said arrangement comprising a data input line for reception of the incoming data stream; data sampling means coupled to the data input line and responsive to the recovered clock output signal for producing as an output a plurality of M clocked samples (RD1, RD2, . . ., RDM) of each data bit from said incoming data stream, M being at least equal to three, one clocked sample located at the approximate midpoint of the data bit and defined as the retimed data output of said clock recovery arrangement, at least one clocked sample located before the midpoint, and at least one other clocked sample located after the midpoint; reference clock means for generating a clock output signal at a predetermined frequency; clock phase generating means responsive to said reference clock output signal for generating a plurality of N clock signals at said predetermined frequency, adjacent clock signals being separated in phase by the amount 360°/N, denoted as phase interval Δφ; and clock phase determination and selection means responsive to both the plurality of M clocked data bit samples from the data sampling means and the plurality of N clock signals from the clock phase generating means for generating as an output the recovered clock signal, said clock phase determination and selection means capable of comparing the logic values of said plurality of M clocked data bit samples and adjusting the phase of the current recovered clock output signal if all do not agree in value, the adjustment being to decrement the phase if the at least one clocked sample after the midpoint is different in value from the others and alternatively to increment the phase if the at least one clocked sample before the midpoint is different in value from the others.

Claim 17

A method of providing a retimed data signal and a recovered clock signal from an incoming digital data signal, the method comprising the steps of: a. providing a reference clock signal at a predetermined frequency; b. sampling the reference clock signal to produce a plurality of N reference clock signals, adjacent clock signals being separated in phase by the amount 360°/N, denoted as a clock phase interval Δφ; c. sampling each bit of the incoming digital data signal to produce a plurality of M data bit samples, one sample being located at the approximate midpoint of the data bit; d. latching the plurality of M data bit samples with the recovered clock signal to produce a plurality of M clocked data bit samples; e. defining the clocked midpoint sample as the retimed data signal; f. comparing the logic values of the plurality of M clocked data bit samples; g. incrementing the phase of the recovered clock signal if clocked data bit samples before the midpoint sample disagree in logic value with the midpoint sample and samples after the midpoint sample; h. decrementing the phase of the recovered clock signal if the clocked data bit samples after the midpoint sample disagree in logic value with the midpoint sample and samples before the midpoint sample; i. repeating steps g. and h. until all data bit samples agree in value.

Claim 18

A method of providing a retimed data signal and a recovered clock signal from an incoming digital data signal, the method comprising the steps of: a. providing a reference clock signal at a predetermined frequency; b. sampling the reference clock signal to produce a plurality of N reference clock signals, adjacent clock signals being separated in phase by the amount 360°/N, denoted as a clock phase interval Δφ; c. sampling each bit of the incoming digital data signal to produce a plurality of M data bit samples, one sample being located at the approximate midpoint of the data bit; d. latching the plurality of M data bit samples with the recovered clock signal to produce a plurality of M clocked data bit samples; e. defining the clocked midpoint sample as the retimed data signal; f. comparing the logic values of the plurality of M clocked data bit samples; g. incrementing the phase of the recovered clock signal if clocked data bit samples before the midpoint sample disagree in logic value with the midpoint sample and samples after the midpoint sample; h. decrementing the phase of the recovered clock signal if the clocked data bit samples after the midpoint sample disagree in logic value with the midpoint sample and samples before the midpoint sample; i. repeating steps g. and h. until all data bit samples agree in value.