US5034967A
Expired / Lapsed
US
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Metastable-free digital synchronizer with low phase error
Assignee: Datapoint Corp
•
Filing: 1988-12-16
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Granted: 1991-07-23
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Expires: 2008-12-16
Abstract
Abstract An output clock signal is synchronized with predetermined phase accuracy relative to an internal stable frequency reference clock signal upon the application of a transition of an asynchronous event signal. A plurality of phase shifted versions of the reference clock signal are derived. Upon the occurrence of the asynchronous signal, the states of the phase shifted versions are sampled, and that information is utilized as a code to select one of the phase shifted versions from which the output clock signal is derived. Synchronization occurs rapidly within the metastable settling time of the flip-flops of a register which sample or decode the states of the phase shifted versions, or by logical gating arrangements which avoid the necessity for considering the metastable signal. Synchronization is typically obtainable in less than the period of one reference clock signal.
Inventors
- 👤 William M. Cox
- 👤 Michael A. Fischer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:11
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; H04L7/0338; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/38; H04L25/40; H04L25/49; H04L25/4917; H04L25/4919
Claims Analysis
Total Claims: 60
Claim 1
Independent Claim
241 words
A synchronizer for supplying a periodic output clock signal which is in synchronism with a periodic reference clock signal and which is phase shifted relative to the reference clock signal by an amount established by reference to the occurrence of an asynchronous signal, comprising: means receptive of the reference clock signal for creating a plurality of digital versions of the reference clock signal which are phase shifted relative to one another over the period of the reference clock signal; means receptive of the phase shifted versions and operative for supplying the phase shifted versions and inversions of the phase shifted versions; and means receptive of the asynchronous signal and the plurality of phase shifted versions and operative for selecting one of the phase shifted versions and inversions thereof from which to derive the output clock signal based on the digital states of the phase shifted versions at the time of the occurrence of the asynchronous signal, said means for selecting one of the phase shifted versions comprising register means receptive of all of the phase shifted versions and operative in response to the asynchronous signal for setting values therein which correspond to the states of the phase shifted versions upon the occurrence of the asynchronous signal, and phase selecting means receptive of the code and operative for determining from the code the one of the phase shifted versions and inversions thereof from which the output clock signal is to be derived.
Claim 2
Dependent Claim
241 words
A synchronizer for supplying a periodic output clock signal which is in synchronism with a periodic reference clock signal and which is phase shifted relative to the reference clock signal by an amount established by reference to the occurrence of an asynchronous signal, comprising: means receptive of the reference clock signal for creating a plurality of digital versions of the reference clock signal which are phase shifted relative to one another over the period of the reference clock signal; means receptive of the phase shifted versions and operative for supplying the phase shifted versions and inversions of the phase shifted versions; and means receptive of the asynchronous signal and the plurality of phase shifted versions and operative for selecting one of the phase shifted versions and inversions thereof from which to derive the output clock signal based on the digital states of the phase shifted versions at the time of the occurrence of the asynchronous signal, said means for selecting one of the phase shifted versions comprising register means receptive of all of the phase shifted versions and operative in response to the asynchronous signal for setting values therein which correspond to the states of the phase shifted versions upon the occurrence of the asynchronous signal, and phase selecting means receptive of the code and operative for determining from the code the one of the phase shifted versions and inversions thereof from which the output clock signal is to be derived.
Claim 3
Dependent Claim
174 words
A synchronizer as for supplying a periodic output clock signal which is in synchronism with a periodic reference clock and which is phase shifted relative to the reference clock signal by an amount established by reference to the occurrence of an asynchronous signal, comprising: means receptive of the reference clock signal for creating a plurality of digital versions of the reference clock signal which are phase shifted relative to one another over the period of the reference clock signal; and means receptive of the asynchronous signal and the plurality of phase shifted versions and operative for selecting one of the phase shifted clock versions from which to derive the output clock signal based on the digital states of the phase shifted clock versions at the time of the occurrence of the asynchronous signal; and wherein the relative phase relationship between the output clock signal and the occurrence of the asynchronous event signal falls within a predetermined range of 0 to one-half of the reference clock period divided by the number of phase shifted versions.
Claim 4
Dependent Claim
174 words
A synchronizer as for supplying a periodic output clock signal which is in synchronism with a periodic reference clock and which is phase shifted relative to the reference clock signal by an amount established by reference to the occurrence of an asynchronous signal, comprising: means receptive of the reference clock signal for creating a plurality of digital versions of the reference clock signal which are phase shifted relative to one another over the period of the reference clock signal; and means receptive of the asynchronous signal and the plurality of phase shifted versions and operative for selecting one of the phase shifted clock versions from which to derive the output clock signal based on the digital states of the phase shifted clock versions at the time of the occurrence of the asynchronous signal; and wherein the relative phase relationship between the output clock signal and the occurrence of the asynchronous event signal falls within a predetermined range of 0 to one-half of the reference clock period divided by the number of phase shifted versions.
Claim 5
Dependent Claim
175 words
A synchronizer for supplying a periodic output clock signal which is in synchronism with a periodic reference clock signal and which is phase shifted relative to the reference clock signal by an amount established by reference to the occurrence of an asynchronous signal, comprising: means receptive of the reference clock signal for creating a plurality of digital versions of the reference clock signal which are phase shifted relative to one another over the period of the reference clock signal; and means receptive of the asynchronous signal and the plurality of phase shifted versions and operative for selecting one of the phase shifted clock versions from which to derive the output clock signal based on the digital states of the phase shifted clock versions at the time of the occurrence of the asynchronous signal; and wherein the relative phase relationship between the output clock signal and and the occurrence of the asynchronous event signal is determined substantially only from the number of phase-shifted clock versions and a maximum time period between any two sequential phase-shifted versions.
Claim 6
Dependent Claim
175 words
A synchronizer for supplying a periodic output clock signal which is in synchronism with a periodic reference clock signal and which is phase shifted relative to the reference clock signal by an amount established by reference to the occurrence of an asynchronous signal, comprising: means receptive of the reference clock signal for creating a plurality of digital versions of the reference clock signal which are phase shifted relative to one another over the period of the reference clock signal; and means receptive of the asynchronous signal and the plurality of phase shifted versions and operative for selecting one of the phase shifted clock versions from which to derive the output clock signal based on the digital states of the phase shifted clock versions at the time of the occurrence of the asynchronous signal; and wherein the relative phase relationship between the output clock signal and and the occurrence of the asynchronous event signal is determined substantially only from the number of phase-shifted clock versions and a maximum time period between any two sequential phase-shifted versions.
Claim 7
Dependent Claim
71 words
A synchronizer as defined in claim 1, 2 or 3 wherein: said means for creating a plurality of phase shifted versions of the reference clock signal comprises a multi-tap delay means, and each tap of the multi-tap delay means supplies at least one phase shifted version; and the time delay between each of the taps of the multi-tap delay means is approximately equal over the period of the reference clock signal.
Claim 8
Dependent Claim
21 words
A synchronizer as defined in claim 4 wherein: the plurality of versions of the reference clock signal is an odd number.
Claim 9
Dependent Claim
51 words
A synchronizer as defined in claim 1 wherein: a selected one of the phase shifted versions or inversions thereof is supplied as the output clock signal; and said phase selecting means uniquely identifies the one of the phase shifted versions or inversions thereof which is supplied as the output clock signal.
Claim 10
Dependent Claim
42 words
A synchronizer as defined in claims 1 or 6 wherein: said phase selecting means further comprises gating means receptive of the set values and operative for deriving on a mutually exclusive basis the one of the phase shifted versions or inversions thereof.
Claim 11
Dependent Claim
22 words
A synchronizer as defined in claim 7 wherein: the gating means is also operative in response to inversions of the set values.
Claim 12
Dependent Claim
23 words
A synchronizer as defined in claim 8 wherein: the gating means is also receptive of the phase shifted versions and the inversions thereof.
Claim 13
Dependent Claim
98 words
A synchronizer as defined in claim 8 further comprising: second gating means in addition to the gating means first aforementioned; and wherein: said first gating means is operative in response to the set values and inversions thereof and is operative to supply a selection control signal which uniquely identifies the one of the phase shifted versions or the inversions thereof; and said second gating means is receptive of the phase shifted versions and inversions thereof and is operative in response to the selection control signal for supplying the selected one of the phase shifted versions or inversions thereof.
Claim 14
Dependent Claim
54 words
A synchronizer as defined in claim 1 or 6 wherein: said phase selecting means further comprises means responsive to the set values and inversions thereof and to the phase shifted versions and inversions thereof and is operative for supplying on a mutually exclusive basis the one of the phase shifted versions or inversions thereof.
Claim 15
Dependent Claim
80 words
A synchronizer as defined in claim 1 wherein: the period of the output clock signal is an integer multiple of the period of the reference clock signal; and said phase selecting means further comprises means responsive to the set values and inversions thereof and to the phase shifted versions and inversions thereof and is operative for supplying on a mutually exclusive basis the one of the phase shifted versions or inversions thereof from which the output clock signal is derived.
Claim 16
Dependent Claim
69 words
A synchronizer as defined in claim 12 further comprising: means responsive to the selected one of the phase shifted versions or inversions thereof and operative for initiating the output clock signal within one period of the reference clock period after the occurrence of the asynchronous signal and for changing states of the output clock signal upon the occurrence of a predetermined number of cycles of the reference clock signal.
Claim 17
Dependent Claim
73 words
A synchronizer as defined in claim 13 wherein said means for initiating the output clock signal and for changing states of the output clock signal, further operatively maintains the output clock signal in one predetermined state during the first cycle of the output clock signal after initiation for a different predetermined number of cycles of the reference clock signal than said one state is maintained during subsequent cycles of the output clock signal.
Claim 18
Dependent Claim
93 words
A synchronizer as defined in claims 1 or 6 further comprising: means receptive of the selected one of phase shifted versions or inversions thereof and operative for supplying the output clock signal at a predetermined frequency which is substantially less than the reference clock signal, the output clock signal supplying means creating a transition in the output clock signal substantially upon the occurrence of the asynchronous signal and thereafter supplying transitions of the output clock signal in coincidence with the transitions of the selected one of the phase shifted versions or inversions thereof.
Claim 19
Dependent Claim
121 words
A synchronizer as defined in claim 1 wherein: said register means comprises a plurality of memory cell means, each memory cell means receiving one phase shifted version and being operative in response to the asynchronous signal to set a value therein corresponding to the state of the phase shifted version at the time of the occurrence of asynchronous signal, each memory cell means further being susceptible to supplying a metastable set value in response to the approximately simultaneous occurrences of a transition of the phase shifted version and the occurrence of the asynchronous signal; and said phase selecting means operatively determines the one phase shifted version from the values set in the register means other than those potentially metastable set values.
Claim 20
Dependent Claim
32 words
A synchronizer as defined in claim 16 further comprising: means for supplying the output clock signal within one period of the reference clock signal after the occurrence of the asynchronous event signal.
Claim 21
Dependent Claim
19 words
A synchronizer as defined in claim 17 wherein no more than one set value is metastable at a time.
Claim 22
Dependent Claim
19 words
A synchronizer as defined in claim 17 wherein no more than two set values are metastable at a time.
Claim 23
Dependent Claim
126 words
A synchronizer as defined in claim 1 wherein: said register means comprises a plurality of memory cell means, each memory cell means receiving one phase shifted version and being operative in response to the asynchronous signal to set a value therein corresponding to the state of the phase shifted version at the time of the occurrence of asynchronous signal, each memory cell means further being susceptible to supplying a metastable set value for a settling time in response to the approximately simultaneous occurrences of a transition of the phase shifted version and the occurrence of the asynchronous signal; and said phase selecting means operatively determines the one phase shifted version from the set values after a predetermined time delay which is greater than the settling time.
Claim 24
Dependent Claim
22 words
A synchronizer as defined in claim 20 wherein the settling time is less than the time delay between subsequent phase shifted versions.
Claim 25
Dependent Claim
23 words
A synchronizer as defined in claim 20 wherein the predetermined time delay is less than the time delay between subsequent phase shifted versions.
Claim 26
Dependent Claim
14 words
A synchronizer as defined in claim 22 wherein the predetermined time delay is constant.
Claim 27
Dependent Claim
46 words
A synchronizer as defined in claim 1, 2 or 3 further comprising: means responsive to the selected one of the phase-shifted versions for deriving and supplying the output clock signal within one period of the reference clock signal after the occurrence of the asynchronous event signal.
Claim 28
Dependent Claim
36 words
A synchronizer as defined in claim 1, 2 or 3 further comprising: means responsive to the selected one of the phase-shifted versions for deriving and supplying the output clock signal within a predetermined constant time delay.
Claim 29
Dependent Claim
25 words
A synchronizer as defined in claim 25 wherein the predetermined constant time delay is independent of the frequency of periodicity of the reference clock signal.
Claim 30
Dependent Claim
28 words
A synchronizer as defined in claim 25 wherein the predetermined constant time delay is independent of any phase relationship between the reference clock signal and the asynchronous signal.
Claim 31
Dependent Claim
47 words
A synchronizer as defined in claim 1, 2 or 3 further comprising: means responsive to the selected one of the phase-shifted versions for deriving and supplying the output clock signal within a time delay which is independent of the frequency of periodicity of the reference clock signal.
Claim 32
Dependent Claim
50 words
A synchronizer as defined in claim 1, 2 or 3 further comprising: means responsive to the selected one of the phase-shifted versions for deriving and supplying the output clock signal within a time delay which is independent of any phase relationship between the reference clock signal and the asynchronous signal.
Claim 33
Dependent Claim
38 words
A synchronizer as defined in claim 1, 2 or 3 wherein: the output clock signal is the selected one of the phase-shifted versions, and said means for selecting the one phase-shifted versions consists essentially of combinatorial logic elements.
Claim 34
Dependent Claim
125 words
A synchronizer as defined in claim 2 or 3 further comprising: a plurality of memory cell means, each memory cell means receiving one phase-shifted version and being operative in response to a transition of the reference clock signal to set a value therein to the state of the phase-shifted version at the time of the occurrence of the transition of the reference clock signal, each memory cell means further being susceptible to supplying a metastable set value in response to the approximately simultaneous occurrences of a transition of the phase-shifted version and the occurrence of the asynchronous signal; and wherein: said phase selecting means operatively selects one of the phase shifted versions from a majority of the set values supplied from the memory cell means.
Claim 35
Dependent Claim
48 words
A synchronizer as defined in claim 31 wherein the transition of the asynchronous signal is one of the rising edge or the falling edge of the asynchronous signal, and the one of the transitions of the asynchronous signal is selected by the previous state of the output signal.
Claim 36
Dependent Claim
34 words
A synchronizer as defined in claim 32 wherein: the output signal is supplied within a predetermined constant time delay which is less than the time period of one period of the reference clock signal.
Claim 37
Dependent Claim
24 words
A synchronizer as defined in claim 1, 2 or 3 wherein: the plurality of versions of the reference clock signal is an odd number.
Claim 38
Dependent Claim
116 words
A synchronizer as defined in claim 2 or 3 further comprising: a plurality of memory cell means, each memory cell means receiving one phase shifted version and being operative in response to the asynchronous signal to set a value therein corresponding to the state of the phase shifted version at the time of the occurrence of asynchronous signal, each memory cell means further being susceptible to supplying a metastable set value in response to the approximately simultaneous occurrences of a transition of the phase shifted version and the occurrence of the asynchronous signal; and said phase selecting means operatively determines the one phase shifted version from the set values other than those potentially metastable set values.
Claim 39
Dependent Claim
32 words
A synchronizer as defined in claim 35 further comprising: means for supplying the output clock signal within one period of the reference clock signal after the occurrence of the asynchronous event signal.
Claim 40
Dependent Claim
19 words
A synchronizer as defined in claim 36 wherein no more than one set value is metastable at a time.
Claim 41
Dependent Claim
19 words
A synchronizer as defined n claim 36 wherein no more than two set values are metastable at a time.
Claim 42
Dependent Claim
125 words
A synchronizer as defined in claim 2 or 3 further comprising: a plurality of memory cell means, each memory cell means receiving one phase shifted version and being operative in response to the asynchronous signal to set a value therein corresponding to the state of the phase shifted version at the time of the occurrence of asynchronous signal, each memory cell means further being susceptible to supplying a metastable set value for a settling time in response to the approximately simultaneous occurrences of a transition of the phase shifted version and the occurrence of the asynchronous signal; and said phase selecting means operatively determines the one phase shifted version from the set values after a predetermined time delay which is greater than the settling time.
Claim 43
Dependent Claim
22 words
A synchronizer as defined in claim 39 wherein the settling time is less than the time delay between subsequent phase shifted versions.
Claim 44
Dependent Claim
23 words
A synchronizer as defined in claim 39 wherein the predetermined time delay is less than the time delay between subsequent phase shifted versions.
Claim 45
Dependent Claim
14 words
A synchronizer as defined in claim 41 wherein the predetermined time delay is constant.
Claim 46
Dependent Claim
38 words
A synchronizer as defined in claim 1, 2 or 3 wherein: the output clock signal is the selected one of the phase-shifted versions, and said means for selecting the one phase-shifted versions comprises essentially only combinatorial logic elements.
Claim 47
Dependent Claim
127 words
A synchronizer as defined in claim 1 wherein: wherein said register means comprises a plurality of memory cell means, each memory cell means receiving one phase-shifted version and being operative in response to a transition of the reference clock signal to set a value therein to the state of the phase-shifted version at the time of the occurrence of the transition of the reference clock signal, each memory cell means further being susceptible to supplying a metastable set value in response to the approximately simultaneous occurrences of a transition of a phase-shifted version and the occurrence of the asynchronous signal; and wherein: said phase selecting means operatively selects one of the phase shifted versions from a majority of the set values supplied from the memory cell means.
Claim 48
Dependent Claim
28 words
A synchronizer as defined in claim 44 wherein the transition of the asynchronous signal is one of the rising edge or the falling edge of the asynchronous signal.
Claim 49
Dependent Claim
27 words
A synchronizer as defined in claim 45 wherein the one of the transitions of the asynchronous signal is selected by the previous state of the output signal.
Claim 50
Dependent Claim
36 words
A synchronizer as defined in claims 45 or 46 wherein: the output signal is supplied within a predetermined constant time delay which is less than the time period of one period of the reference clock signal.
Claim 51
Dependent Claim
53 words
A synchronizer as defined in claim 2 or 3 wherein: a selected one of the phase shifted versions or inversions thereof is supplied as the output clock signal; and said phase selecting means uniquely identifies the one of the phase shifted versions or inversions thereof which is supplied as the output clock signal.
Claim 52
Dependent Claim
42 words
A synchronizer as defined in claims 2 or 3 wherein: said phase selecting means further comprises gating means receptive of the set values and operative for deriving on a mutually exclusive basis the one of the phase shifted versions or inversions thereof.
Claim 53
Dependent Claim
22 words
A synchronizer as defined in claim 49 wherein: the gating means is also operative in response to inversions of the set values.
Claim 54
Dependent Claim
23 words
A synchronizer as defined in claim 50 wherein: the gating means is also receptive of the phase shifted versions and the inversions thereof.
Claim 55
Dependent Claim
98 words
A synchronizer as defined in claim 50 further comprising: second gating means in addition to the gating means first aforementioned; and wherein: said first gating means is operative in response to the set values and inversions thereof and is operative to supply a selection control signal which uniquely identifies the one of the phase shifted versions or the inversions thereof; and said second gating means is receptive of the phase shifted versions and inversions thereof and is operative in response to the selection control signal for supplying the selected one of the phase shifted versions or inversions thereof.
Claim 56
Dependent Claim
54 words
A synchronizer as defined in claims 2 or 3 wherein: said phase selecting means further comprises means responsive to the set values and inversions thereof and to the phase shifted versions and inversions thereof and is operative for supplying on a mutually exclusive basis the one of the phase shifted versions or inversions thereof.
Claim 57
Dependent Claim
82 words
A synchronizer as defined in claim 2 or 3 wherein: the period of the output clock signal is an integer multiple of the period of the reference clock signal; and said phase selecting means further comprises means responsive to the set values and inversions thereof and to the phase shifted versions and inversions thereof and is operative for supplying on a mutually exclusive basis the one of the phase shifted versions or inversions thereof from which the output clock signal is derived.
Claim 58
Dependent Claim
69 words
A synchronizer as defined in claim 54 further comprising: means responsive to the selected one of the phase shifted versions or inversions thereof and operative for initiating the output clock signal within one period of the reference clock period after the occurrence of the asynchronous signal and for changing states of the output clock signal upon the occurrence of a predetermined number of cycles of the reference clock signal.
Claim 59
Dependent Claim
73 words
A synchronizer as defined in claim 54 wherein said means for initiating the output clock signal and for changing states of the output clock signal, further operatively maintains the output clock signal in one predetermined state during the first cycle of the output clock signal after initiation for a different predetermined number of cycles of the reference clock signal than said one state is maintained during subsequent cycles of the output clock signal.
Claim 60
Dependent Claim
93 words
A synchronizer as defined in claims 2 or 3 further comprising: means receptive of the selected one of phase shifted versions or inversions thereof and operative for supplying the output clock signal at a predetermined frequency which is substantially less than the reference clock signal, the output clock signal supplying means creating a transition in the output clock signal substantially upon the occurrence of the asynchronous signal and thereafter supplying transitions of the output clock signal in coincidence with the transitions of the selected one of the phase shifted versions or inversions thereof.
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USPTO Annuity & Maintenance Windows
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| 3.5 Years (Year 4) | 1994-07-22 | 1995-01-21 | 1995-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-22 | 1999-01-21 | 1999-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-22 | 2003-01-21 | 2003-07-23 | $7700.00 | Window Closed / Lapsed |