US3621139A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data receiver with intersymbol interference correction
Assignee: Boeing North American Inc
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Filing: 1970-05-11
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Granted: 1971-11-16
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Expires: 1990-05-11
Abstract
Abstract The system of the present invention utilizes previous digit decisions to correct a large part of the intersymbol interference of a received signal by subtracting the intersymbol interference components of a previously received signal from the received signal. The system is comprised of means for delaying an input digital data signal having intersymbol interference components. A correction means receives the nondelayed and the delayed signal along with a corrected system output signal which is fed back to the correcting means from the system''s output. The correcting means generates from the corrected system''s output signal a new signal containing all bits normally associated with the output signal when it was first received and wherein the generated intersymbol interference signals are subtracted from the delayed and nondelayed input signals to provide corrected signals. The nondelayed signal is fed to an amplifier with a predetermined gain setting. The output from the amplifier and the delayed output from the correction means are summed together in a summing means. A sampler samples the summing means output at substantially the data bit rate. A threshold detector detects the level of the sampled signal to provide the corrected system''s output signal.
Inventors
- 👤 Earl D Gibson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 20:11
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03114; H04L25/03133
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
273 words
A digital data receiver which utilizes previous digit decisions to correct a substantial part of the intersymbol interference contained in a received digital data signal within an interval of a few digit durations comprising in combination: a low-pass filter means for receiving an input digital data signal and for filtering out high-frequency noise components; a delay means for receiving the fiLtered signal from said filter means and for delaying said filtered signal for at least one data baud (or digit) to provide a delayed filtered signal; a correction means for receiving as inputs said delayed filtered signal, said filtered signal and a corrected receiver output signal; said correction means operating upon the corrected receiver output signal to provide two signals equal to the intersymbol interference caused by previously evaluated digits, which signals are subtracted from said delayed filter signal and said filtered signal to eliminate a portion of the intersymbol interference contained in said signals so as to provide a partially corrected filtered signal and a partially corrected delayed filtered signal; amplifier means for amplifying said partially corrected delayed filtered signal by a preselected gain so as to maximize the linear separation between different levels of said received digital data signal; summing means for summing the output signal from said amplifier means with the partially corrected filtered signal; sampling means sampling the output signal from said summing means at substantially the received digit rate; and threshold detector means for determining if the output signal from said sampling means is above or below a predetermined threshold level, feeding the corrected receiver output signal which represents the receivers digit decision back to said correction means.
Claim 2
Dependent Claim
273 words
A digital data receiver which utilizes previous digit decisions to correct a substantial part of the intersymbol interference contained in a received digital data signal within an interval of a few digit durations comprising in combination: a low-pass filter means for receiving an input digital data signal and for filtering out high-frequency noise components; a delay means for receiving the fiLtered signal from said filter means and for delaying said filtered signal for at least one data baud (or digit) to provide a delayed filtered signal; a correction means for receiving as inputs said delayed filtered signal, said filtered signal and a corrected receiver output signal; said correction means operating upon the corrected receiver output signal to provide two signals equal to the intersymbol interference caused by previously evaluated digits, which signals are subtracted from said delayed filter signal and said filtered signal to eliminate a portion of the intersymbol interference contained in said signals so as to provide a partially corrected filtered signal and a partially corrected delayed filtered signal; amplifier means for amplifying said partially corrected delayed filtered signal by a preselected gain so as to maximize the linear separation between different levels of said received digital data signal; summing means for summing the output signal from said amplifier means with the partially corrected filtered signal; sampling means sampling the output signal from said summing means at substantially the received digit rate; and threshold detector means for determining if the output signal from said sampling means is above or below a predetermined threshold level, feeding the corrected receiver output signal which represents the receivers digit decision back to said correction means.
Claim 3
Dependent Claim
48 words
The invention according to claim 1 and further comprising: a subtracting means interposed between said sampling means and said threshold detector means for subtracting the threshold level of said threshold detector from the sampled output signal and further fixing the threshold level of said threshold detector to zero.
Claim 4
Dependent Claim
225 words
A receiver for detecting digital data bits from a distorted waveform input signal which input signal contains digital data bit information and intersymbol interference, comprising in combination: a delay means connected to receive said input signal, said delay means having a plurality of output taps, each separated by a delay equal to one data bit interval, with delayed input signals available to said taps; a correction means for receiving as inputs said delayed input signals said received input signal, and a corrected system output signal, said correction means generating from the corrected output signal a plurality of normalized distorted waveforms containing intersymbol components, one of which normalized waveforms is subtracted from each of said delayed output signals and said input signal, respectively, so as to provide partially corrected delayed output signals and a partially corrected input signal; a first set of amplifier means for amplifying each of said partially corrected delayed signals by preselected gains; means for summing together the output signals from said amplifier means and said partially corrected input signal; means for sampling the amplitude of the summed signal from said summing means at substantially the bit interval; and threshold detector means for determining if the sampled signal is above or below a predetermined amplitude level, and for feeding back a corrected system output signal indicative of the determination to said correction means.
Claim 5
Dependent Claim
225 words
A receiver for detecting digital data bits from a distorted waveform input signal which input signal contains digital data bit information and intersymbol interference, comprising in combination: a delay means connected to receive said input signal, said delay means having a plurality of output taps, each separated by a delay equal to one data bit interval, with delayed input signals available to said taps; a correction means for receiving as inputs said delayed input signals said received input signal, and a corrected system output signal, said correction means generating from the corrected output signal a plurality of normalized distorted waveforms containing intersymbol components, one of which normalized waveforms is subtracted from each of said delayed output signals and said input signal, respectively, so as to provide partially corrected delayed output signals and a partially corrected input signal; a first set of amplifier means for amplifying each of said partially corrected delayed signals by preselected gains; means for summing together the output signals from said amplifier means and said partially corrected input signal; means for sampling the amplitude of the summed signal from said summing means at substantially the bit interval; and threshold detector means for determining if the sampled signal is above or below a predetermined amplitude level, and for feeding back a corrected system output signal indicative of the determination to said correction means.
Claim 6
Dependent Claim
48 words
The invention according to claim 3 and further comprising: a subtracting means interposed between said sampling means and said threshold detector means for subtracting the threshold level of said threshold detector from the sampled output signal and further fixing the threshold level of said threshold detector to zero.
Claim 7
Dependent Claim
111 words
The invention according to claim 3 wherein said previous decision correction means is comprised of: a delay means connected to receive a corrected system output signal, said delay means having a plurality of equally spaced output taps and an attenuator connected to each delay line tap to provide at each tap a signal which is a component of the distorted waveform input signal; means for summinG said tap signals together to form a normalized waveform signal and for subtracting said normalized waveform signal from said delayed input signals and from said received input signal so as to provide said partially corrected delayed output signals and said partially corrected input signal, respectively.
Claim 8
Dependent Claim
155 words
The invention according to claim 3 and further comprising: a second set of amplifier means for amplifying each of said partially corrected delay signals by preselected gains; a second means for summing together the output signals from said second set of amplifier means; a second means for sampling the amplitude of the summed signal from said summing means at substantially the bit interval; a second threshold detector means for determining if the sampled signal from said second sampling means is above or below a second predetermined amplitude level; and amplitude level and logic means receiving the output signals from said first and second threshold detector means and providing an output signal of a first level when the output from either or both detector means is below said predetermined level, and providing an output of a second level when the output from both of said threshold detector means is above the first and second predetermined levels.
Claim 9
Dependent Claim
52 words
The invention according to claim 6 and further comprising: a subtracting means interposed between each of said sampling means and each of said threshold detector means for subtracting the threshold level of said threshold detector from the sampled output signal and further fixing the threshold level of said threshold detector to zero.
References Cited (Backward Citations)
US3368168A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-15 | 1975-05-17 | 1975-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-15 | 1979-05-17 | 1979-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-15 | 1983-05-17 | 1983-11-16 | $7700.00 | Window Closed / Lapsed |