Timing recovery in a digitally implemented data receiver

Claim 2

An improved method of operating a pulse amplitude modulated data receiver which is implemented at least in part by a digital data processor whereby said receiver is able to receive pulse amplitude modulated data signals from a plurality of channels through a common path including an autonomously timed sampling commutator and an analog-to-digital converter, said method comprising the steps of: a. operating said commutator at a frequency such that it samples the signals in each channel at a rate which is a multiple of the nominal rate at which amplitude modulated data pulses are sent through that channel; b. establishing for each sampled pulse a repetitive sequence of regularly timed counting intervals, each having a duration T, the number of such intervals in each repetition of said sequence corresponding to the number of times that each pulse is sampled by said commutator; c. from the set of digital codes produced by said converter in response to the sampling of each pulse by said commutator, determining the timing error, if any, between the instant when said pulse reaches its peak and the time at which a predetermined count in said sequence is reached; d. in response to the determined value of said timing error and the digital codes representing the sampled pulse values, operating said processor in a manner such as to provide at least one digital filter for sequentially generating digital codes to represent the magnitude-versus-time function of each sampled pulse, said filter being so constituted that it causes the production of the digital code representing the peak value of each pulse to occur a selected number of counting intervals in said sequence subsequent to said predetermined count therein; e. establishing a second repetitive sequence of regularly timed counting intervals corresponding in general to the firstmentioned sequence of counting intervals; f. making available at the output of said receiver the digital code produced by said filter each time a particular count in said second sequence is attained; and g. effecting a coincidence between the time at which said particular count is attained and the time at which said filter produces a peak-value-representing code by optionally adjusting the number of intervals in said second sequence at which said particular count will occur and/or adjusting the whole or fractional number of intervals in said first sequence which will elapse between the actual occurrence of said pulse peak and the subsequent production of a peak-value-representing code by said filter.

Claim 3

A receiver operating method as set forth in claim 1 wherein Step d provides a digital filter which performs an interpolation among the coded sample values representing each pulse to ascertain the code representing the peak value of that pulse, and which delays the exit of said peak value code from said filter to coincide with the occurrence of said particular count.

Claim 4

A method as set forth in claim 2 wherein said processor is preconditioned to store various filter coefficients that may be utilized selectively in Step d to provide the digital filter with a chosen delay period L whose value lies between certain minimum and maximum values according to the amount of delay chosen.

Claim 5

A method as set forth in claim 3 in which Step d provides a digital filter having an output/input function F(z) defined by the following equation: F(z) (A2 + A1z 1 + z 2)/(1 + A1z 1 + A2z 2) wherein z k represents a time delay of kT, and A1 and A2 are filter coefficients whose values are related to the chosen value of the delay period L.

Claim 6

A method as set forth in claim 3 in which Step d provides a filter having an output/input function F(z) defined by the following equation: F(z) (p1 - z 1)/(1 - p1z 1) . (p2 - z 1)/(1 - p2z 1) wherein z k represents a time delay of kT, and p1 and p2 are filter coefficients whose values are related to the chosen value of the delay period L.

Claim 7

A method as set forth in claim 3 which includes the steps of detecting when the timing error that is determined in Step C is outside a given range of values, and in response thereto temporarily altering the number of intervals in said second sequence at which said particular count will occur as specified in step f, so that the resulting delay L may be chosen by the selection of available stored filter coefficients.

Claim 8

A method as set forth in claim 3 wherein Step d provides a pair of filters, one of which is supplied with coefficients that are currently in use, and the other of which is supplied with coefficients that next will be needed when the timing error reaches such magnitude that a change in the value of the delay L is needed, the determination as to which filter shall supply the receiver output being made during Step d in response to the determination of the timing error in Step c.

Claim 9

In a digital data receiver for receiving pulse amplitude modulated data signals from a plurality of channels, an improved timing control means for enabling such signals to be received through an analog-to digital converter which is common to all of said channels, notwithstanding any lack of mutual synchronism among the several channels, said improvement comprising: a. an input sampling commutator, whose timing is autonomous with respect to the pulse timing in said channels, interposed between said channels and said converter, said commutator being operable to sample each of the channels at a rate which is a multiple of the pulse frequency in that channel, whereby each sample pulse is represented at the output of said converter by a sequence of digital codes corresponding to the respective sample values; b. a sample counter for maintaining a modular count of the time intervals at which said digital codes are produced by said converter for any given channel, the modulus of such count being the number of samples per pulse; c. a timing error estimator responsive to the digital codes representing the respective sample values for determining the timing error, if any, between the instant when each sampled pulse is at its peak and the time when the sample count for that pulse reached a predetermined value less than said modulus; d. digital filter means effective in response to the sequence of digital codes from said converter which represents each pulse in said given channel to generate a series of output digital codes representing the magnitude-versus-time function of that pulse, including the peak value thereof, said filter means delaying the production of the output code representing said peak value for a period of time determined by the characteristics of said filter means, said timing error estimator controlling the characteristics of said filter means and said sample counter to effect a coincidence between the time at which said filter means produces a peak-value-representing code and the time at which said sample counter attains a particular count subsequent to said predetermined count by optionally adjusting the count number being maintained by said sample counter and/or the delay period effected by said filter means; and e. an output sampliNg switch controlled by said counter for delivering to the output of said receiver in said given channel the digital codes which are produced by said filter means at the times when said sample counter reaches said particular count, thereby effectively correcting any initial errors in pulse timing.

Claim 10

In a digital data receiver for receiving pulse amplitude modulated data signals from a plurality of channels, an improved timing control means for enabling such signals to be received through an analog-to digital converter which is common to all of said channels, notwithstanding any lack of mutual synchronism among the several channels, said improvement comprising: a. an input sampling commutator, whose timing is autonomous with respect to the pulse timing in said channels, interposed between said channels and said converter, said commutator being operable to sample each of the channels at a rate which is a multiple of the pulse frequency in that channel, whereby each sample pulse is represented at the output of said converter by a sequence of digital codes corresponding to the respective sample values; b. a sample counter for maintaining a modular count of the time intervals at which said digital codes are produced by said converter for any given channel, the modulus of such count being the number of samples per pulse; c. a timing error estimator responsive to the digital codes representing the respective sample values for determining the timing error, if any, between the instant when each sampled pulse is at its peak and the time when the sample count for that pulse reached a predetermined value less than said modulus; d. digital filter means effective in response to the sequence of digital codes from said converter which represents each pulse in said given channel to generate a series of output digital codes representing the magnitude-versus-time function of that pulse, including the peak value thereof, said filter means delaying the production of the output code representing said peak value for a period of time determined by the characteristics of said filter means, said timing error estimator controlling the characteristics of said filter means and said sample counter to effect a coincidence between the time at which said filter means produces a peak-value-representing code and the time at which said sample counter attains a particular count subsequent to said predetermined count by optionally adjusting the count number being maintained by said sample counter and/or the delay period effected by said filter means; and e. an output sampliNg switch controlled by said counter for delivering to the output of said receiver in said given channel the digital codes which are produced by said filter means at the times when said sample counter reaches said particular count, thereby effectively correcting any initial errors in pulse timing.

Claim 11

Timing control means as set forth in claim 8 wherein the duration of the peak delay period effected by said filter means depends upon the values of certain coefficients chosen for said filter means, said control means including selector means responsive to the output of said timing error estimator for selecting from among the available sets of filter coefficients those which will provide the required delay period.

Claim 12

Timing control means as set forth in claim 9 wherein said timing error estimator has a controlling relationship to said sample counter for altering the count maintained by said counter when the timing error assumes a value such that it would fall outside the range for which correction could be made by the available filter coefficients in the absence of such count alteration, thereby changing the length of the delay period which must be provided by said filter means so that it can be attained through the selection of available filter coefficients.

Claim 13

Timing control means as set forth in claim 9 wherein said digital filter means includes a pair of filters having different coefficients, only one of said filters having its output coupled to said output sampling switch at any given time, said control means including a filter status switch controlled by said selector means for determining which of said filters should be coupled to said switch whenever a change of coefficients is required, said selector means then being effective to supply the other filter with the coefficients which most probably will be needed when the next change of coefficients occurs.