US3757296A
Expired / Lapsed
US
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Digit error detector
Assignee: Boeing North American Inc
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Filing: 1971-11-15
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Granted: 1973-09-04
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Expires: 1991-11-15
Abstract
Abstract The present invention is a digit error detector for detecting errors in a partial response signalling system wherein digital data signals with an arbitrary number of levels are transmitted through a partial response channel at a baud rate and wherein the received digits have more possible values than the transmitted digits. The digit error detector utilizes a summing means having as an input the signals which are received and sampled by a receiver, which summing means sums these signals with prior received digit signals to provide a present received digit signal at any instant in time the present sampled signal is summed. The prior digit signals are obtained from a feedback means which is connected to the output of the summing means and which feedback means process the present received digit signal in terms of limiting the amplitude of the signal to the maximum amplitude of a possible received signal and by delaying the signal an even multiple of baud intervals before feeding the delayed digit signal back to an input of the summing means. Any errors in the digit signal are then processed around the loop and summed with the most recent signal to provide a signal having an amplitude level above the maximum permitted signal level, the occurrence of which corresponds to an error in the detected signals.
Inventors
- 👤 E Gibson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:34
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/497
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
137 words
An error detector for detecting errors in a partial response signalling system wherein the received digits have more possible values than the transmitted digits and wherein the transmitted digits are transmitted at a baud rate, comprising in combination: a. a summing means having as an input the system''s received digits; b. a feedback means connected to receive the output of said summing means and to limit the amplitude of the received output signal and to delay the output signal an even multiple of baud intervals before feeding the output signal back to an input of said summing means to be summed with the latest received digits; and c. digit level detecting means connected to receive the output signals from said summing means for providing an error signal when the output signals are above a known possible value.
Claim 2
Dependent Claim
137 words
An error detector for detecting errors in a partial response signalling system wherein the received digits have more possible values than the transmitted digits and wherein the transmitted digits are transmitted at a baud rate, comprising in combination: a. a summing means having as an input the system''s received digits; b. a feedback means connected to receive the output of said summing means and to limit the amplitude of the received output signal and to delay the output signal an even multiple of baud intervals before feeding the output signal back to an input of said summing means to be summed with the latest received digits; and c. digit level detecting means connected to receive the output signals from said summing means for providing an error signal when the output signals are above a known possible value.
Claim 3
Dependent Claim
83 words
The error detector according to claim 1 wherein said digit level detecting means is comprised of: a. a first digit level detector connected to receive said output signal for pRoviding a first error signal when the output signal is greater in a positive direction than any possible correct value; and b. a second digit level detector connected to receive said output signal for providing a second error signal when the output signal is greater in a negative direction than any possible correct value.
Claim 4
Dependent Claim
81 words
The error detector according to claim 2 and further comprising: a. a first and a second switch means, each switch means having an odd output terminal and an even output terminal, for connecting the first and second error signals respectively, first to a corresponding odd terminal and second to a corresponding even terminal, said switches operating at the baud rate of the transmitted digits to provide an indication of whether the signals are occurring at an even or odd baud interval.
Claim 5
Dependent Claim
136 words
An error detector for detecting errors in a partial response signalling system wherein the received digits have more possible values than the transmitted digits and wherein the transmitted digits are transmitted at a baud rate, comprising in combination: a. a summing means having as an input the system''s received digits; b. a feedback means connected to receive the output of said summing means and to limit the absolute amplitude of the received output signal and to delay the received output signal for different baud intervals before feeding the delayed signals back to inputs of said summing means to be summed with the latest received digits; and c. digit level detecting means connected to receive the output signals from said summing means for providing an error signal when the output signals are above a known possible value.
Claim 6
Dependent Claim
136 words
An error detector for detecting errors in a partial response signalling system wherein the received digits have more possible values than the transmitted digits and wherein the transmitted digits are transmitted at a baud rate, comprising in combination: a. a summing means having as an input the system''s received digits; b. a feedback means connected to receive the output of said summing means and to limit the absolute amplitude of the received output signal and to delay the received output signal for different baud intervals before feeding the delayed signals back to inputs of said summing means to be summed with the latest received digits; and c. digit level detecting means connected to receive the output signals from said summing means for providing an error signal when the output signals are above a known possible value.
Claim 7
Dependent Claim
99 words
The error detector according to claim 4 wherein said feedback means is comprised of: a. a limiter for receiving the output of said summing means and to limit the absolute amplitude of said output to the largest absolute amplitude of a possible correct value; and b. a multistaged shift register for receiving the signal from said limiter and for delaying said signal through each stage of said shift register wherein each stage corresponds to one baud interval of delay and where the signals present in desired stages of said shift register are fed as inputs to said summing means.
Claim 8
Dependent Claim
83 words
The error detector according to claim 4 wherein said digit level detecting means is comprised of: a. a first digit level detector connected to receive said output signal for providing a first error signal when the output signal is greater in a positive direction than a possible correct value; and b. a second digit level detector connected to receive said output signal for providing a second error signal when the output signal is greater in a negative direction than a possible correct value.
Claim 9
Dependent Claim
186 words
An error detector for detecting errors in a partial response signalling system wherein the received digits are designated Di and have more possible values than the transmitted digits designated di, and wherein the transmitted digits are transmitted at a baud rate, comprising in combination: a. a summing means for summing the received digit estimate Di with a digit estimate d''i 2, which latter digit estimate was made two baud intervals prior to the received digit estimate Di, to form the presently transmitted digit estimate di; b. feedback means connected to receive the output digit estimate di of said summing means and to limit the absolute amplitude of said di signal to the maximum absolute amplitude of the possible transmitted digits and to delay said limited signal two baud intervals to form the signal d''i 2, said feedback means feeding said d''i 2 signal back to an input of said summing means: and c. digit level detecting means connected to receive said di signal from said summing means and to provide An error signal when the amplitude of the di signal is above the known possible values.
Claim 10
Dependent Claim
186 words
An error detector for detecting errors in a partial response signalling system wherein the received digits are designated Di and have more possible values than the transmitted digits designated di, and wherein the transmitted digits are transmitted at a baud rate, comprising in combination: a. a summing means for summing the received digit estimate Di with a digit estimate d''i 2, which latter digit estimate was made two baud intervals prior to the received digit estimate Di, to form the presently transmitted digit estimate di; b. feedback means connected to receive the output digit estimate di of said summing means and to limit the absolute amplitude of said di signal to the maximum absolute amplitude of the possible transmitted digits and to delay said limited signal two baud intervals to form the signal d''i 2, said feedback means feeding said d''i 2 signal back to an input of said summing means: and c. digit level detecting means connected to receive said di signal from said summing means and to provide An error signal when the amplitude of the di signal is above the known possible values.
Claim 11
Dependent Claim
87 words
The error detector according to claim 7 wherein said digit level detecting means is comprised of: a. a first digit level detector connected to receive said digit signal di and for providing a first error signal when the signal, di, is greater in a positive direction than any possible correct value; and b. a second digit level detector connected to receive said digit signal di, and for providing a second error signal when the signal di is greater in a negative direction than any possible correct value.
Claim 12
Dependent Claim
80 words
The error detector according to claim 8 and further comprising: a first and a second switch means, each switch means having an odd output terminal and an even output terminal, for connecting the first and second error signals, respectively, first to a corresponding odd terminal and second to a corresponding even terminal, said switches operating at the baud rate of the transmitted digits to provide an indication of whether the signals are occurring at an even or odd baud interval.
Claim 13
Dependent Claim
210 words
An error detector for detecting errors in partial response signalling system wherein the received digits have more possible values than the transmitted digits, wherein the transmitted digits are transmitted at a baud rate, and wherein the single pulse response of the system establishes for each transmitted pulse a first non-zero amplitude sample and at least one successive non-zero amplitude sample, each such successive sample being delayed relatively to a first sample by a corresponding and predetermined integral multiple of the baud interval, comprising in combination: a. a summing means having an an input the system''s received digits; b. a feedback means connected to receive the output of said summing means and including means to limit the absolute amplitude of the output signal of said summing means, means to delay each said output signal by each said corresponding and predetermined integral multiple of the baud interval, and means to supply each such delayed output signal in a predetermined polarity, in accordance with the single pulse response of the signalling system, to said summing means for combination with each received digit; and c. digit level detecting means connected to receive the output signals from said summing means for providing an error signal when the output signals are above a known possible value.
Claim 14
Dependent Claim
210 words
An error detector for detecting errors in partial response signalling system wherein the received digits have more possible values than the transmitted digits, wherein the transmitted digits are transmitted at a baud rate, and wherein the single pulse response of the system establishes for each transmitted pulse a first non-zero amplitude sample and at least one successive non-zero amplitude sample, each such successive sample being delayed relatively to a first sample by a corresponding and predetermined integral multiple of the baud interval, comprising in combination: a. a summing means having an an input the system''s received digits; b. a feedback means connected to receive the output of said summing means and including means to limit the absolute amplitude of the output signal of said summing means, means to delay each said output signal by each said corresponding and predetermined integral multiple of the baud interval, and means to supply each such delayed output signal in a predetermined polarity, in accordance with the single pulse response of the signalling system, to said summing means for combination with each received digit; and c. digit level detecting means connected to receive the output signals from said summing means for providing an error signal when the output signals are above a known possible value.
Claim 15
Dependent Claim
68 words
An error detector as recited in claim 10 wherein said single pulse response includes only one successive non-zero sample delayed from a first sample by two baud intervals, for each transmitted pulse, and wherein said delay means delays each output signal of said summing means by two baud intervals, and said supply means supplies the delayed output signal in a polarity for additive combination with each received digit.
Claim 16
Dependent Claim
70 words
An error detector as recited in claim 10 wherein said single pulse response includes only one successive non-zero sample delayed from a first sample by a single baud interval, for each transmitted pulse, and wherein said delay means delays each output signal of said summing means by a single baud interval, and said supply means supplies the delayed output signal in a polarity for subtractive combination with each received digit.
Claim 17
Dependent Claim
103 words
An error detector as recited in claim 10 wherein said single pulse response includes three successive non-zero samples delayed from a first sample by one, three and four baud intervals, for each transmitted pulse, and wherein said delay means delays each output signal of said summing means by four successive baud intervals to provide delayed signals of said one, three and four baud intervals of delay, said supply means supplies the delayed output signals in a polarity for subtractive combination, as to the one baud delayed signal, and additive combination as to the three and four baud delAyed signals, with each received digit.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-03 | 1977-03-05 | 1977-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-03 | 1981-03-05 | 1981-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-03 | 1985-03-05 | 1985-09-04 | $7700.00 | Window Closed / Lapsed |