US3746800A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock recovery system
Assignee: Case Communications Inc
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Filing: 1971-08-16
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Granted: 1973-07-17
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Expires: 1991-08-16
Abstract
Abstract A clock recovery circuit for a data communication system, wherein the eye pattern for the data is sampled (by sampling the outputs of the slicer circuits ) and logic circuitry utilized to select only those transitions, i.e., slicer axis crossings, which should be located midway between the desired time sample points and to advance or retard the local clock in accordance with the samples for these transistions. The ratio of advance to retard decisions is utilized to generate, through use of a D to A converter, a control signal for correcting the frequency of the voltage controlled oscillator which serves as the local clock, so that both frequency and phase error correction is provided.
Inventors
- 👤 R Stuart
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:52
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
147 words
A clock recovery circuit for a data communication system comprising clock generator means, a plurality of slicer circuits to which the received data signal is applied, sampling means responsive to said clock generator means for sampling the outputs of said slicer circuits at clock sampling points determined by said clock generator means and at points midway between the clock sampling points, logic circuit means responsive to the output of said sampling means for determining the data signal transitions which cross the slicer circuit decision levels at points approximately midway between the clock sampling points during a sampling interval and for producing a phase control output signal in accordance with the output of the sampling means for said transitions, and means for connecting the output of said logic circuit means to said clock generator means for controlling the output thereof in accordance with said phase control output signal.
Claim 2
Dependent Claim
147 words
A clock recovery circuit for a data communication system comprising clock generator means, a plurality of slicer circuits to which the received data signal is applied, sampling means responsive to said clock generator means for sampling the outputs of said slicer circuits at clock sampling points determined by said clock generator means and at points midway between the clock sampling points, logic circuit means responsive to the output of said sampling means for determining the data signal transitions which cross the slicer circuit decision levels at points approximately midway between the clock sampling points during a sampling interval and for producing a phase control output signal in accordance with the output of the sampling means for said transitions, and means for connecting the output of said logic circuit means to said clock generator means for controlling the output thereof in accordance with said phase control output signal.
Claim 3
Dependent Claim
61 words
A clock recovery circuit as claimed in claim 1 wherein said sampling means comprises a first multivibrator for storing the output of one of said slicer circuits at the baud decision time, a second multivibrator for sampling and storing the output of said one slicer circuit at a time midway between baud decision times, and a third multivibrator for period earlier.
Claim 4
Dependent Claim
146 words
A clock recovery circuit as claimed in claim 2 wherein said data signal is a four level signal, said plurality of slicer circuits comprises inner slicer circuit means for producing a first output when the data signal is less than the decision level thereof and a second output when the data signal is greater than the decision level thereof and outer slicer circuits means for producing a first output when the data signal lies between upper and lower slicer decision levels and for producing a second output when said data signal lies above said upper level or below said lower level, and said sampling comprises a first set of said first, second and third multivibrators for sampling the output of said inner slicer circuit means and a second set of said first, second and third multivibrators for sampling the output of said outer slicer circuit means.
Claim 5
Dependent Claim
56 words
A clock recovery circuit as claimed in claim 1 wherein said logic circuit means comprises electronic gate means responsive to the output of said sampling means for producing, in accordance therewith, an advance pulse for advancing the output of said clock generator means or a retard pulse for retarding the output of said clock generator means.
Claim 6
Dependent Claim
46 words
A clock recovery circuit as claim in claim 4 further comprising a frequency divider chain connected to the output of said clock generator means, the output of said logic circuit means being connected to said frequency divider chain to control the phase of the output thereof.
Claim 7
Dependent Claim
46 words
A clock recover circuit as claimed in claim 4 further comprising integrator means for integrating the output of said electronic gate means over a predetermined time inteval and for producing an output signal in accordance therewith for controlling the frequency output of said clock generator means.
Claim 8
Dependent Claim
85 words
A clock recovery circuit as claimed in claim 6 wherein said clock generator means comprises a variable frequency voltage controlled oscillator and said integrator means comprising counter means for counting the number of advance and retard pulses and for producing an output in accordance with the difference between the number of advance and retard pulses, and digital to analog converter means for converting the output of said counter means into a voltage signal for controlling the frequency output of said variable frequency voltage controlled oscillator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-16 | 1977-01-15 | 1977-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-16 | 1981-01-15 | 1981-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-16 | 1985-01-15 | 1985-07-17 | $7700.00 | Window Closed / Lapsed |