US4896338A — Method and device for the digital synthesis of a …

Claim 1

Independent Claim 187 words

A method for the digital synthesis of a clock signal, of the type wherein the clock signal to be synthesized is obtained from a phase increment datum .sub.ΔP representing the frequency to be synthesized, comprising the steps of performing, at each period T c of a computation clock signal, a binary number M modulo addition of each phase increment with the modulo M sum of the phase increments already totalized inside a phase accumulating device with a capacity equal to the binary number M; reading, after each overflow of the capacity of the accumulator device, the remaining residual phase error P K contained in the accumulating device; generating 2 Q clock signals with a period T c , phase-shifted with respect to each other by T c /2 Q ; computing, after each overflow, the temporal error Δt K by calculating the ratio P K/ΔP between the residual phase error P K and the phase increment ΔP per clock period T c ; and selecting that clock signal for which the phase shift with respect to the computation clock signal is closest to the computed residual phase.

Claim 2

Independent Claim 187 words

A method for the digital synthesis of a clock signal, of the type wherein the clock signal to be synthesized is obtained from a phase increment datum .sub.ΔP representing the frequency to be synthesized, comprising the steps of performing, at each period T c of a computation clock signal, a binary number M modulo addition of each phase increment with the modulo M sum of the phase increments already totalized inside a phase accumulating device with a capacity equal to the binary number M; reading, after each overflow of the capacity of the accumulator device, the remaining residual phase error P K contained in the accumulating device; generating 2 Q clock signals with a period T c , phase-shifted with respect to each other by T c /2 Q ; computing, after each overflow, the temporal error Δt K by calculating the ratio P K/ΔP between the residual phase error P K and the phase increment ΔP per clock period T c ; and selecting that clock signal for which the phase shift with respect to the computation clock signal is closest to the computed residual phase.

Claim 3

Dependent Claim 57 words

A method according to claim 1 wherein the phase shift closest to the computed residual phase is determined from a rounded value q E of the temporal error Δt K , in delaying this value by a value 2 Q representing the period T c of the computing clock signal where Q is a positive whole number.

Claim 4

Dependent Claim 48 words

A method according to claim 2 wherein the ratio between the residual phase error P K and the phase increment ΔP is computed by a digital divider circuit of the pipeline type, the stages of which work at the rate of the computing clock signal T c .

Claim 5

Dependent Claim 19 words

A method according to claim 3 wherein the phase increment is modulated by an increment representing a frequency modulation.

Claim 6

Dependent Claim 23 words

A method according to claim 4 wherein a phase increment representing a phase modulation is added to the content of the accumulating device.

Claim 7

Dependent Claim 38 words

A method according to claim 5 wherein each overflow R KM of the capacity of the accumulating device is indicated by the sign of the difference between two successive values of the residual phase error P K .

Claim 8

Dependent Claim 74 words

A method according to claim 6 wherein, in phase modulation, the phase increment value ΔP KM is obtained at each instant of the computing clock signal by addition of the most recent value of the residual phase error to the phase incremental datum ΔP and by subtraction of the result obtained from the previous value P p of the residual phase error obtained at the computing clock signal instant preceding the current computing instant.

Claim 9

Independent Claim 159 words

A device for the digital synthesis of a clock signal comprising a generator of 2 Q clock signals with a period T c , evenly spaced out in time, two consecutive signals being phase shifted with respect to each other by a quantity T c , a first circuit having a first input coupled to said generator and a second input receiving a phase increment, for making a rough computation of the period of the signal to be synthesized and for determining the residual phase error P k , a second circuit, coupled to said first circuit, for a precise computation of the phase to calculate the ratio P k , and a third circuit for selecting the clock phase coupled to the second circuit and to the generator of the 2 Q clock signals to select the clock signal for which the phase shift with respect to the computation clock signal is closest to the computed residual phase.

Claim 10

Independent Claim 159 words

A device for the digital synthesis of a clock signal comprising a generator of 2 Q clock signals with a period T c , evenly spaced out in time, two consecutive signals being phase shifted with respect to each other by a quantity T c , a first circuit having a first input coupled to said generator and a second input receiving a phase increment, for making a rough computation of the period of the signal to be synthesized and for determining the residual phase error P k , a second circuit, coupled to said first circuit, for a precise computation of the phase to calculate the ratio P k , and a third circuit for selecting the clock phase coupled to the second circuit and to the generator of the 2 Q clock signals to select the clock signal for which the phase shift with respect to the computation clock signal is closest to the computed residual phase.

Claim 11

Dependent Claim 46 words

A device according to claim 8 wherein the first circuit has a phase accumulator to totalize the successive phase increments at each period T c of the computation clock signal and a circuit to give a signal indicating each overflow of the capacity of the accumulator.

Claim 12

Dependent Claim 34 words

A device according to claim 9 wherein the second, precise computation circuit has several adder and subtractor circuits, cascade-mounted in a pipeline structure, to compute the phase shifting value closest to the residual phase.

Claim 13

Dependent Claim 54 words

A device according to claim 10 wherein the clock phase selection circuit has a clock phase decoder, addressed by the phase shift value q c coupled to a validation circuit to select one of the two 2 Q clock signals corresponding to the phase shift q c computed to constitute the synthesized clock signals.

Claim 14

Dependent Claim 102 words

A device according to claim 11 wherein the generator of the 2 Q clock signals has a system of flip-flops arranged in matrix form, each flip-flop giving a clock signal being at the intersection of a line and a column of the matrix organization, each line being coupled to an output among the 2 B outputs of a loop divider, clocked at a frequency F R =2 B times the frequency of the computation clock signal, and each column being coupled to one of 2C direct complement outputs of a device shifting the phase of the clock signal of the loop divider.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1993-01-22	1993-07-24	1994-01-23	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1997-01-22	1997-07-24	1998-01-23	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2001-01-22	2001-07-24	2002-01-23	$7700.00	Window Closed / Lapsed

Method and device for the digital synthesis of a clock signal

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