Lan controller having split bus design

Claim 1

A local area network (LAN) system comprising: (a) a first bus being coupled to a first plurality of units, said first plurality of units including at least a first processor and a first random access memory (RAM), said first RAM for storing procedures for controlling said first processor, said first processor for executing the procedures stored in said first RAM; (b) a second bus being coupled to a second plurality of units which include at least a second RAM, a direct memory access controller (DMA), said second RAM having a first portion for storing user programs for execution on said first processor and a second portion used for simultaneous direct memory access of data to or from said second portion of said second RAM; (c) first means for coupling said first bus to said second bus for separating said first processor and said first RAM from said second processor and said second RAM while permitting the flow of data between said first and second RAMs, and between said first and second processors without interference of program execution by said processors; (d) a third bus being coupled to a third plurality of units which includes at least a third RAM and a third processor; (e) at least one LAN adapter connected to said second bus for interfacing a LAN thereto, and data being transmitted to and from said third RAM and a LAN via said second portion of said second RAM by direct memory access under control of said first processor which controls said DMA controller; and (f) second means for coupling said third bus to said second bus for separating said third RAM and said third processor from said second bus while permitting the flow of data and control signals between said third and said second busses, said control signals being used by said first processor to control transmission of data between said third RAM and said LAN.