Digital phase locked loop having coarse and fine stepsize variable delay lines

Claim 2

A digital phase locked loop as claimed in claim 1, wherein said delay control means (40) comprises: a first timing counter (44; 44A) for counting said reference clock pulse to produce a count and producing a first timing pulse (T1) when the count repeatedly reaches a predetermined value, said first timing pulse defining the start timing of each of said longer intervals; a sequence controller (41) responsive to a first occurrence of said first timing pulse for producing a first enable pulse (EN2, EN1) when the output (PD) of said phase detector (30) has a first logic level, and responsive to a repeated occurrence of said first timing pulse for producing a second enable pulse (EN0) when the output of said phase detector has changed to a second logic level; an up-down counter (42; 42A) arranged to be enabled in response to said first and second enable pulses for counting the reference clock pulse to produce a count value, incrementing or decrementing the count value in accordance with a phase comparison provided by said phase detector (30), and producing from the count value a first group of delay control bits (Z3-Z9; X0-X6) in response to said first enable pulse (EN2, EN1), and a second group of delay control bits (Z3-Z9; X0-X6) and a third group of delay control bits (Z0-Z2; Y0-Y2) in response to said second enable pulse (EN0); a second timing counter (45, 46) responsive to each occurrence of said first timing pulse for counting a delayed clock pulse from said coarse stepsize delay line (11) to produce a count, and producing a second timing pulse (T2) when the count reaches a predetermined value, said second timing pulse defining the end timing of each of said longer intervals; and a latch (43), responsive to said second timing pulse, for latching and forwarding the first and second groups of delay control bits to said coarse stepsize delay line (11) as said higher significant bits and latching and forwarding the third group of control bits to said fine stepsize delay line (12) as said lower significant bits.

Claim 3

A digital phase locked loop as claimed in claim 1, wherein said delay control means (40) comprises: a first timing counter (44; 44A) for counting said reference clock pulse to produce a count and producing a first timing pulse (T1) when the count repeatedly reaches a predetermined value, said first timing pulse defining the start timing of each of said longer intervals; a sequence controller (41) responsive to a first occurrence of said first timing pulse for producing a first enable pulse (EN2) when the output (PD) of said phase detector (30) has a first logic level or a second logic level, responsive to a repeated occurrence of said first timing pulse for producing a second enable pulse (EN1) when the output of said phase detector has changed from said first or second logic level to the second or first level, respectively, and responsive to a further repeated occurrence of said first timing pulse for producing a third enable pulse (EN0) when the output of said phase detector has changed from the logic level at which said second enable pulse (EN1) was produced; an up-down counter (42; 42A) arranged to be enabled in response to said first, second and third enable pulses for counting the reference clock pulse to produce a count value, incrementing or decrementing the count value in accordance with a phase comparison provided by said phase detector (30), and producing from the count value a first group of delay control bits (Z5-Z9; X2-X6) in response to said first enable pulse (EN2), a second group of delay control bits (Z3-Z9; X0-X6) in response to said second enable pulse (EN1), and a third group of delay control bits (Z3-Z9; X0-X6) and a fourth group of delay control bits (Z0-Z2; Y0-Y2) in response to said third enable pulse (EN0); a second timing counter (45, 46) responsive to each occurrence of said first timing pulse for counting a delayed clock pulse from said coarse stepsize delay line (11) to produce a count, and producing a second timing pulse (T2) when the count reaches a predetermined value, said second timing pulse defining the end timing of each of said longer intervals; and a latch (43), responsive to said second timing pulse, for latching and forwarding the first, second and third groups of delay control bits to said coarse stepsize delay line (11) as said higher significant bits and latching and forwarding the fourth group of control bits to said fine stepsize delay line (12) as said lower significant bits.

Claim 4

A digital phase locked loop as claimed in claim 2 or 3, wherein said up-down counter (42) includes means for producing an overflow output (OVF) for resetting said sequence controller (41) to an initialized state when the count value of the up-down counter reaches a full count.

Claim 5

A digital phase locked loop as claimed in claim 4, wherein said sequence controller (41) includes means (440-444) responsive to said overflow output for causing said up-down counter (42) to be initialized to a reset state for a period sufficient for the delayed clock pulse to propagate through said clock tree (20) and starting to produce said enable pulses at the end of said period.

Claim 6

A digital phase locked loop as claimed in claim 4, wherein said first timing counter (44A) is arranged to be loaded with a second full count value (D) when a first full count is reached after said sequence controller (41) is reset to said initialized state, said first timing counter subsequently producing said first timing pulse when said loaded second full count is reached, said second full count value being smaller than said first full count value.

Claim 7

A digital phase locked loop as claimed in claim 2, wherein said up-down counter (42A) includes: a first internal counter (460A) for counting the reference clock pulse to produce a first count value, incrementing or decrementing the first count value in accordance with said phase comparison, and producing from the first count value said third group of delay control bits (Z0-Z2; Y0-Y2), said first internal counter (460A) being arranged to be loaded with a first value (L₁) when the first internal counter produces a carry output and a second value (L₂) when the first internal counter produces a borrow output; and a second internal counter (461, 462) for counting the reference clock pulse to produce a second count value, incrementing or decrementing the second count value in accordance with said phase comparison, and producing from the second count value said first and second groups of delay control bits (Z3-Z9; X0-X6) in response to each one of said carry and borrow outputs.

Claim 8

A digital phase locked loop as claimed in claim 3, wherein said up-down counter (42A) includes: a first internal counter (460A) for counting the reference clock pulse to produce a first count value, incrementing or decrementing the first count value in accordance with said phase comparison, and producing from the first count value said fourth group of delay control bits (Z0-Z2; Y0-Y2), said first internal counter (460A) being arranged to be loaded with a first value (L₁) when the first internal counter produces a carry output and a second value (L₂) when the first internal counter produces a borrow output; a second internal counter (461) for counting the reference clock pulse to produce a second count value, incrementing or decrementing the second count value in accordance with said phase comparison, and producing from the second count value a lower significant subgroup (Z3-Z4; X0-X1) of said second and third groups of delay control bits (Z3-Z9; X0-X6) in response to each one of said carry and borrow outputs of said first internal counter; and a third internal counter (462) for counting the reference clock pulse to produce a third count value, incrementing or decrementing the third count value in accordance with said phase comparison, and producing from the third count value said first group of delay control bits (Z5-Z9; X2-X6) and a higher significant subgroup (Z5-Z9; X2-X6) of said third group of delay' control bits (Z3-Z9; X0-X6) in response to a carry or a borrow output produced by said second internal counter.