US6400735B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Glitchless delay line using gray code multiplexer
Assignee: Xilinx Inc
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Filing: 1998-06-22
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Granted: 2002-06-04
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Expires: 2018-06-22
Abstract
Abstract A glitchless delay line using a Gray code multiplexer is provided. The glitchless delay line combines a multi-tap delay circuit with the Gray code multiplexer. Specifically, the multi-tap delay circuit provides a plurality-of sequentially ordered delayed output signals on a plurality of sequentially ordered output terminals. The Gray code multiplexer has a plurality of input terminals coupled to the sequentially ordered delayed output terminals. The Gray code multiplexer is controlled by driving a Gray code value onto the control terminals of the Gray code multiplexer to select a specific delayed output terminal of the multi-tap delay circuit. The delay provided by the delay line is increased by incrementing the Gray code value on the control terminals of the Gray code multiplexer and decreased by decrementing the Gray code value on the control terminals. Race conditions on the control lines are eliminated when incrementing or decrementing the Gray code value by one.
Inventors
- 👤 Andrew K. Percey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:30
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03K; H03K5/00; H03K5/13; H03K5/133
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
64 words
A delay line, comprising: a multi-tap delay circuit having a plurality of sequentially ordered output terminals; and a Gray code multiplexer having: a plurality of input terminals each coupled to one of the output terminals of the multi-tap delay circuit; a plurality of Gray code control terminals; a multiplexer tree having a first multiplexer level and a last multiplexer level; and an output terminal.
Claim 2
Dependent Claim
64 words
A delay line, comprising: a multi-tap delay circuit having a plurality of sequentially ordered output terminals; and a Gray code multiplexer having: a plurality of input terminals each coupled to one of the output terminals of the multi-tap delay circuit; a plurality of Gray code control terminals; a multiplexer tree having a first multiplexer level and a last multiplexer level; and an output terminal.
Claim 3
Dependent Claim
36 words
The delay line of claim 1 , wherein the Gray code multiplexer is coupled to receive a Gray code value on the Gray code control terminals, the Gray code value selecting one of the input terminals.
Claim 4
Dependent Claim
26 words
The delay line of claim 1 , wherein the last multiplexer level comprises a first multiplexer having a first input terminal and a second input terminal.
Claim 5
Dependent Claim
69 words
The delay line of claim 1 , wherein the first multiplexer level comprises: a second multiplexer having a plurality of sequentially ordered input terminals coupled to a first subset of the sequentially ordered output terminals of the multi-tap delay circuit; and a third multiplexer having a plurality of sequentially ordered input terminals reversedly coupled to a second subset of the sequentially ordered output terminals of the multi-tap delay circuit.
Claim 6
Dependent Claim
22 words
The delay line of claim 1 , wherein the multiplexer tree further comprises a second multiplexer level and a third multiplexer level.
Claim 7
Dependent Claim
31 words
The delay line of claim 1 , wherein the multiplexer tree further comprises a multiplexer tree controller coupled to convert the Gray code value into a plurality of tree select signals.
Claim 8
Dependent Claim
47 words
The delay line of claim 6 , wherein the first multiplexer level comprises a plurality of multiplexers coupled to receive a first subset of the tree select signals; and the last multiplexer level comprises a multiplexer coupled to receive a second subset of the tree select signals.
Claim 9
Dependent Claim
19 words
The delay line of claim 6 , wherein the multiplexer tree controller comprises a plurality of Gray code decoders.
Claim 10
Dependent Claim
25 words
The delay line of claim 1 , further comprising a delay line controller coupled to the Gray code control terminals of the Gray code multiplexer.
Claim 11
Dependent Claim
30 words
The delay line of claim 9 , wherein the delay line controller selects one of the input terminals of the Gray code multiplexer in response to a Gray code value.
Claim 12
Dependent Claim
29 words
The delay line of claim 9 , wherein the delay line controller comprises: a binary up/down counter; and a binary to Gray code converter coupled to the binary counter.
Claim 13
Dependent Claim
131 words
A Gray code multiplexer having a plurality of sequentially ordered input terminals and an output terminal, the Gray code multiplexer comprising: a first multiplexer having a first input terminal, a second input terminal, and an output terminal coupled to the output terminal of the Gray code multiplexer; a second multiplexer having an output terminal coupled to the first input terminal of the first multiplexer and a plurality of sequentially ordered input terminals coupled to a first subset of the sequentially ordered input terminals of the Gray code multiplexer; and a third multiplexer having an output terminal coupled to the second input terminal of the first multiplexer and a plurality of sequentially ordered input terminals reversedly coupled to a second subset of the sequentially ordered input terminals of the Gray code multiplexer.
Claim 14
Dependent Claim
131 words
A Gray code multiplexer having a plurality of sequentially ordered input terminals and an output terminal, the Gray code multiplexer comprising: a first multiplexer having a first input terminal, a second input terminal, and an output terminal coupled to the output terminal of the Gray code multiplexer; a second multiplexer having an output terminal coupled to the first input terminal of the first multiplexer and a plurality of sequentially ordered input terminals coupled to a first subset of the sequentially ordered input terminals of the Gray code multiplexer; and a third multiplexer having an output terminal coupled to the second input terminal of the first multiplexer and a plurality of sequentially ordered input terminals reversedly coupled to a second subset of the sequentially ordered input terminals of the Gray code multiplexer.
Claim 15
Dependent Claim
114 words
The Gray code multiplexer of claim 12 , wherein the first multiplexer further comprises a third input terminal and a fourth input terminal, and the Gray code multiplexer further comprises: a fourth multiplexer having an output terminal coupled to the third input terminal of the first multiplexer and a plurality of sequentially ordered input terminals coupled to a third subset of the sequentially ordered input terminals of the Gray code multiplexer; and a fifth multiplexer having an output terminal coupled to the fourth input terminal of the first multiplexer and a plurality of sequentially ordered input terminals reversedly coupled to a fourth subset of the sequentially ordered input terminals of the Gray code multiplexer.
Claim 16
Dependent Claim
44 words
The Gray code multiplexer of claim 12 , further comprising a multiplexer controller having a plurality of input terminals, a first plurality of output terminals coupled to the second and third multiplexers, and a second plurality of output terminals coupled to the first multiplexer.
Claim 17
Dependent Claim
59 words
The Gray code multiplexer of claim 14 , wherein the multiplexer controller is coupled: to receive a Gray code value on the input terminals of the multiplexer controller; to generate a first plurality of select signals on the first plurality of output terminals; and to generate a second plurality of select signals on the second plurality of output terminals.
Claim 18
Dependent Claim
22 words
The Gray code multiplexer of claim 15 , further comprising a Gray code multiplexer controller coupled to generate the Gray code value.
Claim 19
Dependent Claim
30 words
The Gray code multiplexer of claim 16 , wherein the Gray code multiplexer comprises: a binary up/down counter; and a binary to Gray code converter coupled to the binary counter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-06-03 | 2005-12-03 | 2006-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-06-03 | 2009-12-03 | 2010-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-06-03 | 2013-12-03 | 2014-06-04 | $7700.00 | Window Closed / Lapsed |