Array oscillator circuit

Claim 2

An oscillator circuit, comprising: a ring oscillator having a plurality of interconnected buffer stages; at least a subset of said buffer stages each including: a differential transistor pair having first and second drain outputs and a common source output; a transistor current source coupled to said common source output; and first and second load elements coupled to said first and second drain outputs, respectively, each load element including a set of transistors that together form a load having a substantially symmetric voltage-current characteristic so as to provide high common mode noise rejection; wherein the set of transistors of each said load element includes first and second transistors, and the second transistor of each said load element is diode connected with a gate connected to a drain node of the second transistor; wherein said first and second drain outputs oscillate between voltages of V CC and V C , where V CC is a power supply voltage applied to said buffer stage and V C is an oscillation speed control voltage applied to the first transistor of each of said load elements to control said buffer stage's speed of operation.

Claim 3

The oscillator circuit of claim 1, further including a current source bias circuit that generates a gate voltage for said transistor current source of each buffer stage in said subset of said buffer stages, said current source bias circuit comprising: a half-buffer replica of one of said buffer stages, including one load element, a transistor current source, and an input transistor coupled between the load element and the transistor current source; wherein said half-buffer replica's input transistor has a gate coupled to said V CC power supply voltage, said half-buffer replica generating an output signal; a differential amplifier having first and second inputs, said first input coupled to said half-buffer replica so as to receive said half-buffer replica's output signal and said second input coupled to said V C speed control voltage, said differential amplifier generating as an output a bias control voltage V B that is coupled to the transistor current sources of said half-buffer replica and said buffer stages, wherein said differential amplifier is coupled to said half-replica buffer in a negative feedback arrangement such that the bias control voltage V B is automatically adjusted until said half-buffer replica's output signal has a voltage substantially equal to said oscillation speed control voltage V C ; wherein said current source bias circuit automatically adjusts said bias control voltage V B such that each said buffer circuit's current usage remains substantially unchanged due to small variations in said power supply voltage V CC .

Claim 4

The oscillator circuit of claim 2, said current source bias circuit including: a current mirror for supplying to the differential amplifier a current equal to current used by one said buffer stage.

Claim 5

The oscillator circuit of claim 2, including: a second buffer replica circuit having a load element, a transistor current source, and an input transistor coupled between the load element and the transistor current source; wherein said second buffer replica's input transistor has a gate coupled to said V CC power supply voltage, and said transistor current source has a gate coupled to said bias control voltage V B , said second buffer replica circuit generating an output signal comprising an internal oscillation speed control signal V IC , wherein said internal oscillation speed control signal V IC has a voltage equal to said speed control signal voltage V C and is coupled to said load elements of said buffer stages such that said speed control signal V C is protected from capacitive coupling of noise to said internal oscillation speed control signal V IC .

Claim 6

The oscillator circuit of claim 1, wherein the first and second transistors of each said load element are equally sized.

Claim 7

The oscillator circuit of claim 5, where said oscillation speed control voltage V C is applied to said first transistor in each said load element to control said buffer stage's speed of operation; and wherein said second transistor in each said load element is diode connected with a gate connected to a drain node of said second transistor.

Claim 8

The oscillator circuit of claim 1, wherein the first and second transistors of each said load element are equally sized PMOS transistors.

Claim 9

The oscillator circuit of claim 7, where said oscillation speed control voltage V C is applied to said first transistor in each said load element to control said buffer stage's speed of operation; and wherein said second transistor in each said load element is diode connected with a gate connected to a drain node of said second transistor.

Claim 10

The oscillator circuit of claim 1, further including a current source bias circuit that generates a gate voltage for said transistor current source of each buffer stage in said subset of said buffer stages, said current source bias circuit comprising: a buffer replica that replicates at least a portion of one of said buffer stages, said buffer replica including a load element, a transistor current source, and an input transistor coupled between the load element and the transistor current source; wherein said buffer replica's input transistor has a gate coupled to said V CC power supply voltage, said buffer replica generating an output signal; a differential amplifier having first and second inputs, said first input coupled to said buffer replica so as to receive said buffer replica's output signal and said second input coupled to said V C speed control voltage, said differential amplifier generating as an output a bias control voltage V B that is coupled to the transistor current sources of said buffer replica and said buffer stages, wherein said differential amplifier is coupled to said replica buffer in a negative feedback arrangement such that the bias control voltage V B is automatically adjusted until said buffer replica's output signal has a voltage substantially equal to said V C speed control voltage; wherein said current source bias circuit automatically adjusts said bias control voltage V B such that each said buffer circuit's current usage remains substantially unchanged due to small variations in said power supply voltage V CC .

Claim 11

The oscillator circuit of claim 9, said current source bias circuit including: a current mirror for supplying to the differential amplifier a current equal to current used by one said buffer stage.

Claim 12

The oscillator circuit of claim 9, including: a second buffer replica circuit having a transistor current source with a gate coupled to said bias control voltage V B , said second buffer replica circuit generating an output signal comprising an internal oscillation speed control signal V IC , wherein said internal oscillation speed control signal V IC has a voltage equal to said speed control signal voltage V C and is coupled to said load elements of said buffer stages such that said speed control signal V C is protected from capacitive coupling of noise to said internal oscillation speed control signal V IC .

Claim 13

A delay circuit, comprising: a plurality of interconnected buffer stages; at least a subset of said buffer stages each including: a differential transistor pair having first and second drain outputs and a common source output; a transistor current source coupled to said common source output; and first and second load elements coupled to said first and second drain outputs, respectively, each said load element including a set of transistors that together form a load having a substantially symmetric voltage-current characteristic so as to provide high common mode noise rejection; wherein the set of transistors of each said load element includes first and second transistors, and the second transistor of each said load element is diode connected with a gate connected to a drain node of the second transistor; wherein said first and second drain outputs range between voltages of V CC and V C , where V CC is a power supply voltage applied to said buffer stage and V C is a speed control voltage applied to the first transistor of each of said load elements to control said buffer stage's speed of operation.

Claim 14

A delay circuit, comprising: a plurality of interconnected buffer stages; at least a subset of said buffer stages each including: a differential transistor pair having first and second drain outputs and a common source output; a transistor current source coupled to said common source output; and first and second load elements coupled to said first and second drain outputs, respectively, each said load element including a set of transistors that together form a load having a substantially symmetric voltage-current characteristic so as to provide high common mode noise rejection; wherein the set of transistors of each said load element includes first and second transistors, and the second transistor of each said load element is diode connected with a gate connected to a drain node of the second transistor; wherein said first and second drain outputs range between voltages of V CC and V C , where V CC is a power supply voltage applied to said buffer stage and V C is a speed control voltage applied to the first transistor of each of said load elements to control said buffer stage's speed of operation.

Claim 15

The delay circuit of claim 12, further including a current source bias circuit that generates a gate voltage for said transistor current source of each buffer stage in said subset of said buffer stages, said current source bias circuit comprising: a half-buffer replica of one of said buffer stages, including a load element, a transistor current source, and an input transistor coupled between the load element and the transistor current source; wherein said half-buffer replica's input transistor has a gate coupled to said V CC power supply voltage, said half-buffer replica generating an output signal; a differential amplifier having first and second inputs, said first input coupled to said half-buffer replica so as to receive said half-buffer replica's output signal and said second input coupled to said V C speed control voltage, said differential amplifier generating as an output a bias control voltage V B that is coupled to the transistor current sources of said half-buffer replica and said buffer stages, wherein said differential amplifier is coupled to said half-replica buffer in a negative feedback arrangement such that the bias control voltage V B is automatically adjusted until said half-buffer replica's output signal has a voltage substantially equal to said speed control voltage V C ; wherein said current source bias circuit automatically adjusts said bias control voltage V B such that each said buffer circuit's current usage remains substantially unchanged due to small variations in said power supply voltage V CC .

Claim 16

The delay circuit of claim 13, said current source bias circuit including: a current mirror for supplying to the differential amplifier a current equal to current used by one said buffer stage.

Claim 17

The delay circuit of claim 13, including: a second buffer replica circuit having a load element, a transistor current source, and an input transistor coupled between the load element and the transistor current source; wherein said second buffer replica's input transistor has a gate coupled to said V CC power supply voltage, and said transistor current source has a gate coupled to said bias control voltage V B , said second buffer replica circuit generating an output signal comprising an internal speed control signal V IC , wherein said internal speed control signal V IC has a voltage equal to said speed control signal voltage V C and is coupled to said load element of said buffer stages such that said speed control signal V C is protected from capacitive coupling of noise to said internal speed control signal V IC .

Claim 18

The delay circuit of claim 12, wherein said the first and second transistors of each of said load elements are equally sized.

Claim 19

The delay circuit of claim 16, where said oscillation speed control voltage V C is applied to said first transistor in each said load element to control said buffer stage's speed of operation; and wherein said second transistor in each said load element is diode connected with a gate connected to a drain node of said second transistor.

Claim 20

The delay circuit of claim 12, wherein the first and second transistors of each said load elements are equally sized.

Claim 21

The delay circuit of claim 18, where said oscillation speed control voltage V C is applied to said first transistor in' each said load element to control said buffer stage's speed of operation; and wherein said second transistor in each said load element is diode connected with a gate connected to a drain node of said second transistor.

Claim 22

The delay circuit of claim 12, further including a current source bias circuit that generates a gate voltage for said transistor current source of each buffer stage in said subset of said buffer stages, said current source bias circuit comprising: a buffer replica that replicates at least a portion of one of said buffer stages, said buffer replica including a load element, a transistor current source, and an input transistor coupled between the load element and the transistor current source; wherein said buffer replica's input transistor has a gate coupled to said V CC power supply voltage, said buffer replica generating an output signal; a differential amplifier having first and second inputs, said first input coupled to said buffer replica so as to receive said buffer replica's output signal and said second input coupled to said V C speed control voltage, said differential amplifier generating as an output a bias control voltage V B that is coupled to the transistor current sources of said buffer replica and said buffer stages, wherein said differential amplifier is coupled to said replica buffer in a negative feedback arrangement such that the bias control voltage V B is automatically adjusted until said buffer replica's output signal has a voltage substantially equal to said V C speed control voltage; wherein said current source bias circuit automatically adjusts said bias control voltage V B such that each said buffer circuit's current usage remains substantially unchanged due to small variations in said power supply voltage V CC .

Claim 23

The delay circuit of claim 20, said current source bias circuit including: a current mirror for supplying to the differential amplifier a current equal to current used by one said buffer stage.

Claim 24

The delay circuit of claim 20, including: a second buffer replica circuit having a transistor current source with a gate coupled to said bias control voltage V B , said second buffer replica circuit generating an output signal comprising an internal speed control signal V IC , wherein said internal speed control signal V IC has a voltage equal to said speed control signal voltage V C and is coupled to said load elements of said buffer stages such that said speed control signal V C is protected from capacitive coupling of noise to said internal speed control signal V IC .