EP1049257A2
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Phase selection circuit
Assignee: Microsemi Communications Inc
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Filing: 2000-03-09
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Granted: —
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Expires: 2020-03-09
Abstract
Abstract Phase selection circuit for selecting a phase from signal source generating a multi-phase clock signal is implemented utilizing a single stage of multiplexing gates for receiving taps from signal source, thus minimizing mismatch between phases. Multiplexing gates, connected together at their outputs, select between a tap and an inverse tap and are always left on. The outputs from multiplexing gates are analog summed together to create a single phase output signal which may be shifted in phase by one tap simply by inverting one of the input taps to a multiplexing gate, thus reducing glitching at output signal. Phase interpolation is provided for by further phase shifting the output in steps smaller than one tap utilizing multiplexor circuit which interpolates in multiple steps between a tap and inverse tap. Phase selection circuit provides maximum bandwidth capability, while minimizing mismatch and glitching.
Inventors
- 👤 Greg Warwar
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 05:01
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/131
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
55 words
A phase selection circuit for selecting a phase from a signal source
generating phase signals, comprising: a single stage of multiplexor circuits for receiving phase signals of said
signal source, wherein said multiplexor circuits are connected together their outputs and
said phase is shifted by inverting one of said phase signals to said multiplexor circuit.
Claim 2
Dependent Claim
22 words
The phase selection circuit claimed in claim 1, wherein said multiplexor
circuits are activated during entire operation of said phase selection circuit.
Claim 3
Dependent Claim
15 words
The phase selection circuit claimed in claim 1, wherein said phase signals
comprise delay taps.
Claim 4
Dependent Claim
21 words
The phase selection circuit claimed in claim 3, wherein each of said delay
taps comprises a tap and an inverse tap.
Claim 5
Dependent Claim
29 words
The phase selection circuit claimed in claim 4, wherein each of said
multiplexor circuits comprises a 2 x 1 multiplexor circuit for receiving said tap and said
inverse tap.
Claim 6
Dependent Claim
25 words
The phase selection circuit claimed in claim 3, wherein phase adjustment
accomplished by selectively inverting one of said delay taps from its previous tap
position.
Claim 7
Dependent Claim
20 words
The phase selection circuit claimed in claim 4, wherein said multiplexor
circuits select between said tap and said inverse tap.
Claim 8
Dependent Claim
14 words
The phase selection circuit claimed in 1, wherein said signal source
comprises an oscillator.
Claim 9
Dependent Claim
23 words
The phase selection circuit claimed in 8, wherein said phase selection
circuit selects phase signals off generally equally spaced taps from said oscillator.
Claim 10
Dependent Claim
23 words
The phase selection circuit claimed in claim 3, wherein said multiplexor
circuits interpolate in multiple steps between said tap and said inverse tap.
Claim 11
Dependent Claim
26 words
The phase selection circuit claimed in claim 10, wherein said multiplexor
circuits are modified to select in fractional amounts how much each its inputs is
selected.
Claim 12
Dependent Claim
25 words
The phase selection circuit claimed in claim 10, wherein phase adjustment
accomplished by shifting phase of said output signal in steps smaller than one tap.
Claim 13
Dependent Claim
18 words
The phase selection circuit claimed in claim 10, wherein said multiplexor
circuits are utilized as multiple state gates.
Claim 14
Dependent Claim
20 words
The phase selection circuit claimed in claim 10, wherein said multiplexor
circuits are implemented in CMOS current mode logic technology.
Claim 15
Independent Claim
48 words
A method for selecting a phase, comprising: generating a plurality of phase signals; receiving said plurality of phase signals using a single stage of multiplexor
circuits connected together at their outputs; and inverting one of said plurality of phase signals to said multiplexor circuit
to elect said phase.
Claim 16
Dependent Claim
22 words
The method claimed in claim 15, further comprising the step of: activating said multiplexor circuits are activated during entire phase
election operation.
Claim 17
Dependent Claim
13 words
The method claimed in claim 15, wherein said phase signals comprise
delay taps.
Claim 18
Dependent Claim
19 words
The method claimed in claim 17, wherein each of said delay taps
comprises a tap and an inverse tap.
Claim 19
Dependent Claim
27 words
The method claimed in claim 15, wherein each of said multiplexor circuits
comprises a 2 x 1 multiplexor circuit for receiving said tap and said inverse tap.
Claim 20
Dependent Claim
39 words
The method claimed in claim 15, wherein said step of inverting one of said
plurality of phase signals to said multiplexor circuit to select said phase further
comprises the step of: selecting between a tap and an inverse tap.
Claim 21
Dependent Claim
43 words
The method claimed in claim 15, wherein said step of inverting one of said
plurality of phase signals to said multiplexor circuit to select said phase further
comprises the step of: selectively inverting one of said delay taps from its previous tap position.
Claim 22
Independent Claim
29 words
The method claimed in 15, wherein said step of generating a plurality of
base signals further comprises the step of: generating a plurality of phase signals utilizing an oscillator.
Claim 23
Independent Claim
41 words
The method claimed in 22, wherein said step of inverting one of said
plurality of phase signals to said multiplexor circuit to select said phase further
comprises the step of: selecting phase signals off generally equally spaced taps from said
oscillator.
Claim 24
Dependent Claim
42 words
The method claimed in claim 15, wherein said step of inverting one of said
plurality of phase signals to said multiplexor circuit to select said phase further
comprises the step of: interpolating in multiple steps between a tap and an inverse tap.
Claim 25
Dependent Claim
46 words
The method claimed in claim 24, wherein said step of inverting one of said
plurality of phase signals to said multiplexor circuit to select said phase further
comprises the step of: selecting in fractional amounts how much each of inputs to said
multiplexor circuit is selected.
Claim 26
Dependent Claim
43 words
The method claimed in claim 24, wherein said step of inverting one of said
plurality of phase signals to said multiplexor circuit to select said phase further
comprises the step of: shifting phase of said output signal in steps smaller than one tap.
Claim 27
Dependent Claim
16 words
The method claimed in claim 24, wherein said multiplexor circuits are
utilized as multiple state gates.
Claim 28
Dependent Claim
18 words
The method claimed in claim 24, wherein said multiplexor circuits are
implemented in CMOS current mode logic technology.
References Cited (Backward Citations)
No citation records indexed.
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