US6534781B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact
Assignee: Ovonyx Memory Technology LLC
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Filing: 2000-12-26
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Granted: 2003-03-18
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Expires: 2020-12-26
Abstract
Abstract The invention relates to a process of forming a phase-change memory device. The process includes forming a salicide structure in peripheral logic portion of the substrate and preventing forming salicide structures in the memory array. The device may include a double-wide trench into which a single film is deposited but two isolated lower electrodes are formed therefrom. Additionally a diode stack is formed that communicates to the lower electrode.
Inventors
- 👤 Charles Dennison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:27
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/30; H10D48/32; H10D48/366; H10B; H10B63/00; H10B63/20; H10B63/80; H10N; H10N70/00; H10N70/011; H10N70/20; H10N70/231; H10N70/801; H10N70/821; H10N70/826; H10N70/841; H10N70/8413; H10N70/881; H10N70/882; H10N70/8828
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
93 words
An embedded phase-change memory array comprising: spaced apart first and second active areas that are disposed in a substrate; a CMOS logic structure that is peripheral to the memory array, wherein the CMOS logic structure comprises self-aligned silicide structures disposed over and above doped active areas; a recess comprising a bottom and walls, wherein the recess communicates to the first active area and the second active area; and a polysilicon film disposed in the recess, wherein the polysilicon film has a first conductivity at the bottom and a second conductivity at the walls.
Claim 2
Dependent Claim
93 words
An embedded phase-change memory array comprising: spaced apart first and second active areas that are disposed in a substrate; a CMOS logic structure that is peripheral to the memory array, wherein the CMOS logic structure comprises self-aligned silicide structures disposed over and above doped active areas; a recess comprising a bottom and walls, wherein the recess communicates to the first active area and the second active area; and a polysilicon film disposed in the recess, wherein the polysilicon film has a first conductivity at the bottom and a second conductivity at the walls.
Claim 3
Dependent Claim
69 words
The embedded phase-change memory array according to claim 1 , wherein the first and second active areas are spaced apart along a first symmetry line, further comprising: a third active area that is spaced apart from the first active area along a second symmetry line that is orthogonal to the first symmetry line, wherein the polysilicon film is continuous between the first active area and the second active area.
Claim 4
Dependent Claim
28 words
The embedded phase-change memory array according to claim 1 , further comprising: a first isolation structure that is disposed in the substrate parallel to the second symmetry line.
Claim 5
Dependent Claim
43 words
The embedded phase-change memory array according to claim 1 , further comprising: a first isolation structure that is disposed in the substrate parallel to the second symmetry line; and a trench that is disposed in the substrate orthogonal to the first isolation structure.
Claim 6
Independent Claim
162 words
An apparatus comprising: a dedicated memory chip including a plurality of first address lines and a plurality of second address lines on a substrate, addressing circuitry coupled to the plurality of first address lines and the plurality of second address lines, a plurality of memory cells formed between respective ones of the plurality of first address lines and the plurality of second address lines each memory cell including a spaced apart first active area and second active area disposed in the substrate and a recess in the substrate including a bottom and walls, a CMOS logic structure that is peripheral to the plurality of memory cells, and a polysilicon film disposed in the recess, wherein the polysilicon film has a first conductivity at the bottom and a second conductivity at the walls, wherein the CMOS logic structure includes self-aligned silicide structures disposed over and above doped active areas, wherein the recess communicates to the first active area and the second active area.
Claim 7
Independent Claim
162 words
An apparatus comprising: a dedicated memory chip including a plurality of first address lines and a plurality of second address lines on a substrate, addressing circuitry coupled to the plurality of first address lines and the plurality of second address lines, a plurality of memory cells formed between respective ones of the plurality of first address lines and the plurality of second address lines each memory cell including a spaced apart first active area and second active area disposed in the substrate and a recess in the substrate including a bottom and walls, a CMOS logic structure that is peripheral to the plurality of memory cells, and a polysilicon film disposed in the recess, wherein the polysilicon film has a first conductivity at the bottom and a second conductivity at the walls, wherein the CMOS logic structure includes self-aligned silicide structures disposed over and above doped active areas, wherein the recess communicates to the first active area and the second active area.
Claim 8
Dependent Claim
71 words
The apparatus according to claim 5 , wherein the first and second active areas are spaced apart along a first symmetry line, each memory cell further including a third active area in the substrate that is spaced apart from first active area along a second symmetry line that is orthogonal to the first symmetry line, wherein the polysilicon film is continuous between the first active area and the second active area.
Claim 9
Dependent Claim
29 words
The apparatus according to claim 6 , wherein each memory cell further includes a first isolation structure that is disposed in the substrate parallel to the second symmetry line.
Claim 10
Dependent Claim
27 words
The apparatus according to claim 7 , wherein each memory cell further includes a trench that is disposed in the substrate orthogonal to the first isolation structure.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-03-17 | 2006-09-16 | 2007-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-03-17 | 2010-09-16 | 2011-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-03-17 | 2014-09-16 | 2015-03-18 | $7700.00 | Window Closed / Lapsed |