Field-effect transistor based on embedded cluster structures and process for its production

Claim 2

Field-effect transistor, with a semiconductor substrate made of a first semiconductor material, a cluster layer, in which a plurality of semiconductor clusters made of a second semiconductor material different from the first semiconductor material are arranged on the substrate and are at least partially surrounded by the first semiconductor material, wherein the crystal configuration of the semiconductor clusters is in an elastically or partially elastically relaxed state thereby causing a three-dimensional strain field in the surrounding first semiconductor material, source and drain regions which extend vertically at least to a channel region, whereby at least one part of the semiconductor cluster extends laterally between sections that lie below or within the source/drain regions, a channel region that is formed from the aforementioned part of the semiconductor cluster and/or from a layer of said first semiconductor material possibly deposited above said part of the semiconductor cluster, wherein the crystal configuration of the said layer is in a strained state caused by the three-dimensional strain field or fields of the at least partially surrounded and at least partially elastically relaxed clusters, and a gate electrode formed above the channel region.

Claim 3

Field-effect transistor according to claim 1 , characterized in that the first semiconductor material is silicon, the second semiconductor material is Si x Ge 1−x (0≦X<1).

Claim 4

Field-effect transistor according to claim 1 , characterized in that the first semiconductor material is GaAs, the second semiconductor material is InGaAs.

Claim 5

Field-effect transistor according to claim 1 , characterized in that on the cluster layer, a layer of the first semiconductor material is formed, which layer has the sections forming the channel region made of a strained first semiconductor material, which extend from the source region to the drain region and which lie above said part of the semiconductor cluster.

Claim 6

Field-effect transistor according to claim 4 , characterized in that an additional cluster layer is formed on the layer of the first semiconductor material, in which cluster layer a large number of semiconductor clusters are arranged on the layer of the first semiconductor material and are surrounded by the first semiconductor material.

Claim 7

Field-effect transistor according to claim 4 , characterized in that an alternating sequence of additional cluster layers and layers of the first semiconductor material formed thereon is arranged on the layer of the first semiconductor material, whereby the cluster layers are formed in each case in that a plurality of semiconductor clusters is arranged on the underlying layer of the first semiconductor material.

Claim 8

Field-effect transistor according to claim 6 , characterized in that the source and drain regions extend vertically to the uppermost layer of the first semiconductor material.

Claim 9

Field-effect transistor according to claim 6 , characterized in that the source and drain regions extend vertically to a deeper lying, possibly to the lowest layer of the first semiconductor material.

Claim 10

Field-effect transistor according to claim 1 , characterized in that the channel region is formed by semiconductor clusters that extend from the source region to the drain region.

Claim 11

Field-effect transistor according to claim 9 , characterized in that the gate electrode is formed directly above the cluster layer.

Claim 12

Field-effect transistor according to claim 9 , characterized in that a layer of the first semiconductor material is formed on the cluster layer such that the cluster layer is formed as a buried layer.

Claim 13

Field-effect transistor according to claim 1 , characterized in that it is designed as a MODFET structure.

Claim 14

Field-effect transistor according to claim 1 , characterized in that the semiconductor clusters are arranged linearly in the at least one cluster layer.

Claim 15

Field-effect transistor according to claim 13 , characterized in that a plurality of cluster layers are stacked one on top of another and the lines of the semiconductor clusters are arranged on top of each other.

Claim 16

A CMOS semiconductor device comprising: a p-type semiconductor substrate; an NMOS transistor having: NMOS transistor n-type doped source and drain zones provided in an NMOS transistor surface region of the p-type semiconductor substrate and extending to a depth from the NMOS transistor surface region, an NMOS transistor gate electrode overlying the NMOS transistor surface region with an NMOS transistor gate dielectric layer therebetween, an NMOS transistor n-type channel region disposed in the p-type semiconductor substrate under the NMOS transistor gate electrode and interposed between the *NMOS transistor n-type doped source and drain zones, and an NMOS cluster layer disposed in the p-type semiconductor substrate adjacent the NMOS transistor n-type channel region and interposed between the NMOS transistor n-type doped source and drain zones, the NMOS cluster layer being configured in an elastically or partially elastically relaxed state to generate a three-dimensional strain field in the adjacent NMOS transistor n-type channel region; and a PMOS transistor having: PMOS transistor p-type doped source and drain zones provided in a PMOS transistor surface region of a n-type well disposed in the p-type semiconductor substrate, the PMOS transistor p-type doped source and drain zones extending to a depth from the PMOS transistor surface region, a PMOS transistor gate electrode overlying the PMOS transistor surface region with a PMOS transistor gate dielectric layer therebetween, and a PMOS transistor p-type channel region disposed in the n-type well under the PMOS transistor gate electrode and interposed between the PMOS transistor p-type doped source and drain zones, the PMOS transistor p-type channel region being formed by a PMOS transistor cluster layer disposed in the n-type well and interposed between the PMOS transistor p-type doped source and drain zones.

Claim 17

A CMOS semiconductor device comprising: a p-type semiconductor substrate; an NMOS transistor having: NMOS transistor n-type doped source and drain zones provided in an NMOS transistor surface region of the p-type semiconductor substrate and extending to a depth from the NMOS transistor surface region, an NMOS transistor gate electrode overlying the NMOS transistor surface region with an NMOS transistor gate dielectric layer therebetween, an NMOS transistor n-type channel region disposed in the p-type semiconductor substrate under the NMOS transistor gate electrode and interposed between the *NMOS transistor n-type doped source and drain zones, and an NMOS cluster layer disposed in the p-type semiconductor substrate adjacent the NMOS transistor n-type channel region and interposed between the NMOS transistor n-type doped source and drain zones, the NMOS cluster layer being configured in an elastically or partially elastically relaxed state to generate a three-dimensional strain field in the adjacent NMOS transistor n-type channel region; and a PMOS transistor having: PMOS transistor p-type doped source and drain zones provided in a PMOS transistor surface region of a n-type well disposed in the p-type semiconductor substrate, the PMOS transistor p-type doped source and drain zones extending to a depth from the PMOS transistor surface region, a PMOS transistor gate electrode overlying the PMOS transistor surface region with a PMOS transistor gate dielectric layer therebetween, and a PMOS transistor p-type channel region disposed in the n-type well under the PMOS transistor gate electrode and interposed between the PMOS transistor p-type doped source and drain zones, the PMOS transistor p-type channel region being formed by a PMOS transistor cluster layer disposed in the n-type well and interposed between the PMOS transistor p-type doped source and drain zones.

Claim 18

The CMOS transistor according to claim 15 , wherein the p-type semiconductor substrate and the n-type well are silicon and the NMOS cluster layer and the PMOS cluster a layer are Si x Ge 1−x (0≦X<1).

Claim 19

The CMOS transistor according to claim 15 , wherein the p-type semiconductor substrate and the n-type well are GaAs and the NMOS cluster layer and the PMOS cluster layer are InGaAs.

Claim 20

The CMOS transistor according to claim 15 , further comprising an alternating sequence of one or more additional NMOS n-type channel regions and one or more respective adjacent NMOS cluster layers disposed in the substrate under the NMOS transistor gate electrode and interposed between the NMOS transistor n-type doped source and drain zones.

Claim 21

An NMOS transistor comprising: a p-type semiconductor substrate; NMOS transistor n-type doped source and drain zones provided in an NMOS transistor surface region of the p-type semiconductor substrate and extending to a depth from the NMOS transistor surface region; an NMOS transistor gate electrode overlying the NMOS transistor surface region with an NMOS transistor gate dielectric layer therebetween; an NMOS transistor n-type channel region disposed in the p-type semiconductor substrate under the NMOS transistor gate electrode and interposed between the NMOS transistor n-type doped source and drain zones; and an NMOS cluster layer disposed in the p-type semiconductor substrate adjacent the NMOS transistor n-type channel region and interposed between the NMOS transistor n-type doped source and drain zones, the NMOS cluster layer being configured in an elastically or partially elastically relaxed state to generate a three-dimensional strain field in the adjacent NMOS transistor n-type channel region.

Claim 22

An NMOS transistor comprising: a p-type semiconductor substrate; NMOS transistor n-type doped source and drain zones provided in an NMOS transistor surface region of the p-type semiconductor substrate and extending to a depth from the NMOS transistor surface region; an NMOS transistor gate electrode overlying the NMOS transistor surface region with an NMOS transistor gate dielectric layer therebetween; an NMOS transistor n-type channel region disposed in the p-type semiconductor substrate under the NMOS transistor gate electrode and interposed between the NMOS transistor n-type doped source and drain zones; and an NMOS cluster layer disposed in the p-type semiconductor substrate adjacent the NMOS transistor n-type channel region and interposed between the NMOS transistor n-type doped source and drain zones, the NMOS cluster layer being configured in an elastically or partially elastically relaxed state to generate a three-dimensional strain field in the adjacent NMOS transistor n-type channel region.

Claim 23

The NMOS transistor according to claim 19 , wherein the p-type semiconductor substrate is silicon and the NMOS cluster layer is Si x Ge 1−x (0≦X<1).

Claim 24

The NMOS transistor according to claim 19 , wherein the p-type semiconductor substrate is GaAs, and the NMOS cluster layer is InGaAs.

Claim 25

The NMOS transistor according to claim 19 , further comprising an alternating sequence of one or more additional NMOS n-type channel regions and one or more respective adjacent NMOS cluster layers disposed in the p-type semiconductor substrate under the NMOS transistor gate electrode and interposed between the NMOS transistor n-type doped source and drain zones.

Claim 26

A PMOS transistor comprising: an n-type semiconductor substrate; PMOS transistor p-type doped source and drain zones provided in a PMOS transistor surface region of the n-type semiconductor substrate and extending co a depth from the PMOS transistor surface region; a PMOS transistor gate electrode overlying the PMOS transistor surface region with a PMOS transistor gate dielectric layer therebetween; a PMOS transistor p-type channel region disposed in the n-type semiconductor substrate under the PMOS transistor gate electrode and interposed between the PMOS transistor p-type doped source and drain zones; and a PMOS cluster layer disposed in the n-type semiconductor substrate adjacent the PMOS transistor p-type channel region and interposed between the PMOS transistor p-type doped source and drain zones, the PMOS cluster layer being configured in an elastically or partially elastically relaxed state to generate a three-dimensional strain field in the adjacent PMOS transistor p-type channel region.

Claim 27

A PMOS transistor comprising: an n-type semiconductor substrate; PMOS transistor p-type doped source and drain zones provided in a PMOS transistor surface region of the n-type semiconductor substrate and extending co a depth from the PMOS transistor surface region; a PMOS transistor gate electrode overlying the PMOS transistor surface region with a PMOS transistor gate dielectric layer therebetween; a PMOS transistor p-type channel region disposed in the n-type semiconductor substrate under the PMOS transistor gate electrode and interposed between the PMOS transistor p-type doped source and drain zones; and a PMOS cluster layer disposed in the n-type semiconductor substrate adjacent the PMOS transistor p-type channel region and interposed between the PMOS transistor p-type doped source and drain zones, the PMOS cluster layer being configured in an elastically or partially elastically relaxed state to generate a three-dimensional strain field in the adjacent PMOS transistor p-type channel region.

Claim 28

The PMOS transistor according to claim 23 , wherein the n-type semiconductor substrate is silicon and the PMOS cluster layer is Si x Ge 1−x (0<X≦1).

Claim 29

The PMOS transistor according to claim 23 , wherein the n-type semiconductor substrate is GaAs, and the PMOS cluster layer is InGaAs.

Claim 30

The PMOS transistor according to claim 23 , further comprising an alternating sequence of one or more additional PMOS p-type channel regions and one or more respective adjacent PMOS cluster layers disposed in the n-type semiconductor substrate under the PMOS transistor gate electrode and interposed between the PMOS transistor p-type doped source and drain zones.