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EP0921575A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Semiconductor device comprising a heterostructure MIS field-effect transistor having a strained channel layer

Assignee: Panasonic Holdings Corp
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Filing: 1998-12-02
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Granted: —
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Expires: 2018-12-02
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Abstract

Abstract A MISFET having extremely high mobility comprising a first silicon layer (Si layer)(12), a silicon layer containing carbon (Si 1-y C y layer)(13) and an optional, second silicon layer (Si layer)(14) stacked in this order on a silicon substrate (10). The carbon content and thickness of the Si 1-y C y layer acting as a channel layer of the MISFET are such that said Si 1-y C y layer is under tensile strain whereby the conduction and valence bands thereof are split. Therefore, charge carriers having a smaller effective mass, which have been induced by an electric field applied to an insulated gate electrode (15,16), are confined in the Si 1-y C y layer, and move in the channel direction. Furthermore, if the silicon layer containing carbon is made of Si 1-x-y Ge x C y , a structure suitable for a high-performance CMOS device can be formed. Alternatively, the silicon layers may contain a slight amount of carbon or germanium, and a Schottky gate may be provided whereby a MESFET is achieved.

Inventors

  • 👤 Takeshi Takagi

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-30 11:07
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/40; H10D30/47; H10D30/471; H10D30/475; H10D30/473; H10D30/751; H10D30/791; H10D30/798; H10D30/80; H10D30/801; H10D62/00; H10D62/80; H10D62/83; H10D62/832

Claims Analysis

Total Claims: 24
Claim 1
Independent Claim 74 words
A semiconductor device comprising a field effect transistor on a substrate, the field effect transistor including: a first silicon layer formed on the substrate; a second silicon layer, which is formed on the first silicon layer, contains carbon and has received a tensile strain from the first silicon layer; and a gate electrode formed over the second silicon layer, wherein the second silicon layer functions as a channel region of the field effect transistor.
Claim 2
Dependent Claim 29 words
The semiconductor device of Claim 1, wherein the field effect transistor is an n-channel field effect transistor, and wherein the second silicon layer is an n-channel where electrons move.
Claim 3
Dependent Claim 27 words
The semiconductor device of Claim 2, wherein electrons are confined by a heterobarrier formed between the first and second silicon layers of the n-channel field effect transistor.
Claim 4
Dependent Claim 34 words
The semiconductor device of Claim 2, further comprising a heavily doped layer, which is formed in the first silicon layer in the vicinity of the second silicon layer and contains a high-concentration n-type dopant.
Claim 5
Dependent Claim 15 words
The semiconductor device of Claim 3, wherein the second silicon layer is a quantum well.
Claim 6
Dependent Claim 59 words
The semiconductor device of Claim 2, further comprising a third silicon layer, which is formed on the second silicon layer and under the gate electrode and applies a tensile strain to the second silicon layer, wherein electrons are confined in the second silicon layer by a potential well formed in a boundary between the second and third silicon layers.
Claim 7
Dependent Claim 34 words
The semiconductor device of Claim 6, further comprising a heavily doped layer, which is formed in the third silicon layer in the vicinity of the second silicon layer and contains a high-concentration n-type dopant.
Claim 8
Dependent Claim 66 words
The semiconductor device of Claim 2, further comprising a third silicon layer, which is formed on the second silicon layer and under the gate electrode and applies a tensile strain to the second silicon layer, wherein electrons are confined in the second silicon layer by a heterobarrier formed between the first and second silicon layers and another heterobarrier formed between the second and third silicon layers.
Claim 9
Dependent Claim 29 words
The semiconductor device of Claim 1, wherein the field effect transistor is a p-channel field effect transistor, and wherein the second silicon layer is a p-channel where holes move.
Claim 10
Dependent Claim 27 words
The semiconductor device of Claim 9, wherein holes are confined by a heterobarrier formed between the first and second silicon layers of the p-channel field effect transistor.
Claim 11
Dependent Claim 34 words
The semiconductor device of Claim 9, further comprising a heavily doped layer, which is formed in the first silicon layer in the vicinity of the second silicon layer and contains a high-concentration p-type dopant.
Claim 12
Dependent Claim 15 words
The semiconductor device of Claim 9, wherein the second silicon layer is a quantum well.
Claim 13
Dependent Claim 59 words
The semiconductor device of Claim 9, further comprising a third silicon layer, which is formed on the second silicon layer and under the gate electrode and applies a tensile strain to the second silicon layer, wherein holes are confined in the second silicon layer by a potential well formed in a boundary between the second and third silicon layers.
Claim 14
Dependent Claim 34 words
The semiconductor device of Claim 13, further comprising a heavily doped layer, which is formed in the third silicon layer in the vicinity of the second silicon layer and contains a high-concentration p-type dopant.
Claim 15
Dependent Claim 67 words
The semiconductor device of Claim 9, further comprising a third silicon layer, which is formed on the second silicon layer and under the gate electrode and applies a tensile strain to the second silicon layer, wherein holes are confined in the second silicon layer defined by a heterobarrier formed between the first and second silicon layers and another heterobarrier formed between the second and third silicon layers.
Claim 16
Dependent Claim 17 words
The semiconductor device of Claim 1, further comprising a gate insulating film formed under the gate electrode.
Claim 17
Dependent Claim 34 words
The semiconductor device of Claim 1, wherein the thickness of the second silicon layer is smaller than a critical thickness, which is determined by the composition of carbon and above which dislocations are generated.
Claim 18
Dependent Claim 14 words
The semiconductor device of Claim 1, wherein the second silicon layer further contains germanium.
Claim 19
Dependent Claim 100 words
The semiconductor device of Claim 1, wherein the field effect transistor is an n-channel field effect transistor in which the second silicon layer is an n-channel, and wherein the semiconductor device further comprises a p-channel field effect transistor including: a fourth silicon layer formed on the substrate; a fifth silicon layer, which is formed on the fourth silicon layer, contains carbon and has received a tensile strain from the fourth silicon layer; and a gate electrode formed over the fifth silicon layer, the fifth silicon layer functioning as a p-channel region, whereby the semiconductor device functions as a complementary device.
Claim 20
Dependent Claim 40 words
The semiconductor device of Claim 19, wherein carbon contained in the second silicon layer of the n-channel field effect transistor has an equal composition to that of carbon contained in the fifth silicon layer of the p-channel field effect transistor.
Claim 21
Dependent Claim 18 words
The semiconductor device of Claim 19, further comprising a gate insulating film formed just under the gate electrode.
Claim 22
Dependent Claim 34 words
The semiconductor device of Claim 19, wherein the thickness of the fifth silicon layer is smaller than a critical thickness, which is determined by the composition of carbon and above which dislocations are generated.
Claim 23
Dependent Claim 16 words
The semiconductor device of Claim 19, wherein the second and fifth silicon layers further contain germanium.
Claim 24
Dependent Claim 28 words
The semiconductor device of Claim 23, wherein germanium contained in the second silicon layer has an equal composition to that of germanium contained in the fifth silicon layer.

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