Method for novel SOI DRAM BICMOS NPN

Claim 1

A method of simultaneously processing array and bipolar areas on a silicon on insulator (SOI) substrate for forming array devices and bipolar devices on the SOI substrate, comprising the steps of: a) providing an SOI substrate having areas thereon to be processed as array regions and other areas thereon to be processed as bipolar regions; b) forming electrically isolated silicon regions in the SOI substrate including array silicon in the array regions and bipolar silicon in the bipolar regions; c) blocking the array silicon including forming a first type dopant collector layer in the bipolar silicon and a base layer in the bipolar silicon on the collector layer; d) unblocking the array silicon and forming a blocking layer on the bipolar silicon including well implanting a second type dopant into the array silicon; e) forming a dielectric layer on the array silicon; f) simultaneously forming a gate layer over the array silicon and over the bipolar silicon; g) forming a cover layer over the gate layer; h) removing the gate layer and the cover layer, except from over a portion of the each array silicon in the array regions; i) forming sidewall spacers on the gate layer and the cover layer on the portion of each array silicon in the array regions; j) removing the blocking layer on the bipolar silicon and masking a portion of each bipolar silicon region; k) simultaneously implanting the first type dopant into the array silicon that is not blocked by the cover layer and sidewall spacers for forming diffusing regions on opposite sides of the gate layer, and into the bipolar silicon that is not masked for forming collector contacts for the collector layer in the bipolar silicon; and l) forming an emitter layer on the base layer.

Claim 2

A method of simultaneously processing array and bipolar areas on a silicon on insulator (SOI) substrate for forming array devices and bipolar devices on the SOI substrate, comprising the steps of: a) providing an SOI substrate having areas thereon to be processed as array regions and other areas thereon to be processed as bipolar regions; b) forming electrically isolated silicon regions in the SOI substrate including array silicon in the array regions and bipolar silicon in the bipolar regions; c) blocking the array silicon including forming a first type dopant collector layer in the bipolar silicon and a base layer in the bipolar silicon on the collector layer; d) unblocking the array silicon and forming a blocking layer on the bipolar silicon including well implanting a second type dopant into the array silicon; e) forming a dielectric layer on the array silicon; f) simultaneously forming a gate layer over the array silicon and over the bipolar silicon; g) forming a cover layer over the gate layer; h) removing the gate layer and the cover layer, except from over a portion of the each array silicon in the array regions; i) forming sidewall spacers on the gate layer and the cover layer on the portion of each array silicon in the array regions; j) removing the blocking layer on the bipolar silicon and masking a portion of each bipolar silicon region; k) simultaneously implanting the first type dopant into the array silicon that is not blocked by the cover layer and sidewall spacers for forming diffusing regions on opposite sides of the gate layer, and into the bipolar silicon that is not masked for forming collector contacts for the collector layer in the bipolar silicon; and l) forming an emitter layer on the base layer.

Claim 5

A method of simultaneously processing array and bipolar areas on a silicon on insulator (SOI) substrate, comprising the steps of: a) providing an SOI substrate having areas thereon to be processed as array regions and other areas thereon to be processed as bipolar regions; b) forming electrically isolated silicon regions in the SOI substrate including array silicon in the array regions and bipolar silicon in the bipolar regions; c) blocking the array silicon including forming a first type dopant collector layer in the bipolar silicon and a base layer in the bipolar silicon on the collector layer; d) unblocking the array silicon and forming a blocking layer on the bipolar silicon including well implanting a second type dopant into the array silicon; e) forming a dielectric layer on the array silicon; f) simultaneously forming a gate layer over the array silicon and over the bipolar silicon; g) forming a cover layer over the gate layer; h) removing the gate layer and the cover layer, except from over a portion of the each array silicon in the array regions; i) forming sidewall spacers on the gate layer and the cover layer on the portion of each array silicon in the array regions; j) removing the blocking layer on the bipolar silicon and masking a portion of each bipolar silicon region; k) simultaneously implanting the first type dopant into the array silicon that is not blocked by the cover layer and sidewall spacers for forming diffusing regions on opposite sides of the gate layer, and into the bipolar silicon that is not masked for forming collector contacts for the collector layer in the bipolar silicon; l) simultaneously forming an inter level dielectric (ILD) layer over the array silicon and over the bipolar silicon, including forming a mask layer on the ILD layer; m) forming openings at least through the mask layer down to the array silicon and the sidewall spacers in the array regions, and down to the base layer in the bipolar regions; and n) depositing silicon in the openings down to the array silicon in the array regions for forming array access lines in the array regions and down to the base layer in the bipolar regions for forming emitters.

Claim 6

A method of simultaneously processing array and bipolar areas on a silicon on insulator (SOI) substrate, comprising the steps of: a) providing an SOI substrate having areas thereon to be processed as array regions and other areas thereon to be processed as bipolar regions; b) forming electrically isolated silicon regions in the SOI substrate including array silicon in the array regions and bipolar silicon in the bipolar regions; c) blocking the array silicon including forming a first type dopant collector layer in the bipolar silicon and a base layer in the bipolar silicon on the collector layer; d) unblocking the array silicon and forming a blocking layer on the bipolar silicon including well implanting a second type dopant into the array silicon; e) forming a dielectric layer on the array silicon; f) simultaneously forming a gate layer over the array silicon and over the bipolar silicon; g) forming a cover layer over the gate layer; h) removing the gate layer and the cover layer, except from over a portion of the each array silicon in the array regions; i) forming sidewall spacers on the gate layer and the cover layer on the portion of each array silicon in the array regions; j) removing the blocking layer on the bipolar silicon and masking a portion of each bipolar silicon region; k) simultaneously implanting the first type dopant into the array silicon that is not blocked by the cover layer and sidewall spacers for forming diffusing regions on opposite sides of the gate layer, and into the bipolar silicon that is not masked for forming collector contacts for the collector layer in the bipolar silicon; l) simultaneously forming an inter level dielectric (ILD) layer over the array silicon and over the bipolar silicon, including forming a mask layer on the ILD layer; m) forming openings at least through the mask layer down to the array silicon and the sidewall spacers in the array regions, and down to the base layer in the bipolar regions; and n) depositing silicon in the openings down to the array silicon in the array regions for forming array access lines in the array regions and down to the base layer in the bipolar regions for forming emitters.

Claim 9

A method of simultaneously processing array and bipolar areas on a silicon on insulator (SOI) substrate, comprising the steps of: a) providing an SOI substrate having areas thereon to be processed as array regions and other areas thereon to be processed as bipolar regions; b) forming electrically isolated silicon regions in the SOI substrate including array silicon in the array regions and bipolar silicon in the bipolar regions; c) blocking the array silicon including forming a first type dopant collector layer in the bipolar silicon and a base layer in the bipolar silicon on the collector layer; d) unblocking the array silicon and forming a blocking layer on the bipolar silicon including well implanting a second type dopant into the array silicon; e) forming a dielectric layer on the array silicon; f) simultaneously forming a gate layer over the array silicon and over the bipolar silicon; g) forming a cover layer over the gate layer; h) removing the gate layer and the cover layer, except from over a portion of the each array silicon in the array regions; i) forming sidewall spacers on the gate layer and the cover layer on the portion of each array silicon in the array regions; j) removing the blocking layer on the bipolar silicon and masking a portion of each bipolar silicon region; k) simultaneously implanting the first type dopant into the array silicon that is not blocked by the cover layer and sidewall spacers for forming diffusing regions on opposite sides of the gate layer, and into the bipolar silicon that is not masked for forming collector contacts for the collector layer in the bipolar silicon; l) simultaneously forming an inter level dielectric (ILD) layer over the array silicon and over the bipolar silicon, including forming a mask layer on the ILD layer; m) forming openings at least through the mask layer down to the array silicon and the sidewall spacers in the array regions, and down to the base layer in the bipolar regions; and n) implanting second type dopant through the openings into the array silicon for forming diffusion regions on opposite sides of the gate layer, and into the base layer for forming base contacts.

Claim 10

A method of simultaneously processing array and bipolar areas on a silicon on insulator (SOI) substrate, comprising the steps of: a) providing an SOI substrate having areas thereon to be processed as array regions and other areas thereon to be processed as bipolar regions; b) forming electrically isolated silicon regions in the SOI substrate including array silicon in the array regions and bipolar silicon in the bipolar regions; c) blocking the array silicon including forming a first type dopant collector layer in the bipolar silicon and a base layer in the bipolar silicon on the collector layer; d) unblocking the array silicon and forming a blocking layer on the bipolar silicon including well implanting a second type dopant into the array silicon; e) forming a dielectric layer on the array silicon; f) simultaneously forming a gate layer over the array silicon and over the bipolar silicon; g) forming a cover layer over the gate layer; h) removing the gate layer and the cover layer, except from over a portion of the each array silicon in the array regions; i) forming sidewall spacers on the gate layer and the cover layer on the portion of each array silicon in the array regions; j) removing the blocking layer on the bipolar silicon and masking a portion of each bipolar silicon region; k) simultaneously implanting the first type dopant into the array silicon that is not blocked by the cover layer and sidewall spacers for forming diffusing regions on opposite sides of the gate layer, and into the bipolar silicon that is not masked for forming collector contacts for the collector layer in the bipolar silicon; l) simultaneously forming an inter level dielectric (ILD) layer over the array silicon and over the bipolar silicon, including forming a mask layer on the ILD layer; m) forming openings at least through the mask layer down to the array silicon and the sidewall spacers in the array regions, and down to the base layer in the bipolar regions; and n) implanting second type dopant through the openings into the array silicon for forming diffusion regions on opposite sides of the gate layer, and into the base layer for forming base contacts.

Claim 14

A method of operating a bitline sense amplifier system including true and complement bitlines coupled to true and complement bitline sense amplifier nodes, comprising: connecting a dynamic sense preamplifier between said nodes; operating the dynamic sense preamplifier in a first amplification signal phase; connecting a CMOS latch between said nodes; and operating the CMOS latch in a second bitline amplifying phase.

Claim 15

A method of operating a bitline sense amplifier system including true and complement bitlines coupled to true and complement bitline sense amplifier nodes, comprising: connecting a dynamic sense preamplifier between said nodes; operating the dynamic sense preamplifier in a first amplification signal phase; connecting a CMOS latch between said nodes; and operating the CMOS latch in a second bitline amplifying phase.