US5021852A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit device
Assignee: Texas Instruments Inc
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Filing: 1989-05-18
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Granted: 1991-06-04
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Expires: 2009-05-18
Abstract
Abstract This invention relates to a semiconductor integrated circuit device which has an insulated-gate type element part comprising a capacitor which is formed through the use of a trench in a semiconductor layer, wherein a low-resistance buried layer is formed in the semiconductor layer prior to forming the trench so that the trench is formed to be surrounded by the low-resistance buried layer and thereby the low-resistance buried layer is used as an electrode of the capacitor.
Inventors
- 👤 Shunichi Sukegawa
- 👤 Takashi Inui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 04:11
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10B; H10B12/00; H10B12/30; H10B12/37
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
318 words
A semiconductor integrated circuit device comprising: semiconductor substrate means of one conductivity type; said semiconductor substrate means of said one conductivity type being provided with a plurality of vertical trenches extending thereinto form the top surface thereof and disposed in spaced relationship with respect to each other; a memory cell including a capacitor and a field-effect transistor provided in one portion of said semiconductor substrate means; a bipolar transistor provided in another portion of said semiconductor substrate means adjacent to the portion thereof in which said memory cell is disposed; a buried semiconductor layer of the other conductivity type embedded in said semiconductor substrate means in spaced relation to the top surface thereof and common to the memory cell and the bipolar transistor as provided in said semiconductor substrate means; the memory cell included in said semiconductor substrate means having at least one of said plurality of vertical trenches, said at least one vertical trench penetrating said buried semiconductor layer of the other conductivity type and bottoming into said semiconductor substrate means of said one conductivity type below said buried semiconductor layer of the other conductivity type; a liner of insulation material bounding the vertical trench included in the memory cell; conductive material filling the vertical trench included in the memory cell and spaced from said semiconductor substrate means and said buried semiconductor layer embedded therein by said insulation liner interposed therebetween; said conductive material, said insulation liner and said buried semiconductor layer defining a trench capacitor of said memory cell in which said conductive material and said buried semiconductor layer are capacitor plates and the insulation liner is a dielectric layer therebetween; and a pair of vertical trenches of said plurality of vertical trenches being disposed on opposite sides of said bipolar transistor provided in said semiconductor substrate means, each of said pair of vertical trenches being filled with insulation material to electrically isolate said bipolar transistor.
Claim 2
Dependent Claim
318 words
A semiconductor integrated circuit device comprising: semiconductor substrate means of one conductivity type; said semiconductor substrate means of said one conductivity type being provided with a plurality of vertical trenches extending thereinto form the top surface thereof and disposed in spaced relationship with respect to each other; a memory cell including a capacitor and a field-effect transistor provided in one portion of said semiconductor substrate means; a bipolar transistor provided in another portion of said semiconductor substrate means adjacent to the portion thereof in which said memory cell is disposed; a buried semiconductor layer of the other conductivity type embedded in said semiconductor substrate means in spaced relation to the top surface thereof and common to the memory cell and the bipolar transistor as provided in said semiconductor substrate means; the memory cell included in said semiconductor substrate means having at least one of said plurality of vertical trenches, said at least one vertical trench penetrating said buried semiconductor layer of the other conductivity type and bottoming into said semiconductor substrate means of said one conductivity type below said buried semiconductor layer of the other conductivity type; a liner of insulation material bounding the vertical trench included in the memory cell; conductive material filling the vertical trench included in the memory cell and spaced from said semiconductor substrate means and said buried semiconductor layer embedded therein by said insulation liner interposed therebetween; said conductive material, said insulation liner and said buried semiconductor layer defining a trench capacitor of said memory cell in which said conductive material and said buried semiconductor layer are capacitor plates and the insulation liner is a dielectric layer therebetween; and a pair of vertical trenches of said plurality of vertical trenches being disposed on opposite sides of said bipolar transistor provided in said semiconductor substrate means, each of said pair of vertical trenches being filled with insulation material to electrically isolate said bipolar transistor.
Claim 3
Dependent Claim
147 words
A semiconductor integrated circuit device as set forth in claim 1, wherein the field-effect transistor of said memory cell includes spaced source and drain regions of the other conductivity type disposed in said semiconductor substrate means and opening onto the top surface thereof; the portion of said semiconductor substrate means of said one conductivity type disposed between said source and drain regions of the other conductivity type defining a channel region; a gate electrode of conductive material disposed above said channel region; a layer of insulation material interposed between said gate electrode and said channel region and defining a gate insulator; and a region of the other conductivity type disposed in said semiconductor substrate means of one conductivity type and extending between said source region and said buried semiconductor layer of the other conductivity type to connect said field-effect transistor to said capacitor of said memory cell.
Claim 4
Dependent Claim
42 words
A semiconductor integrated circuit device as set forth in claim 2, wherein said region of the other conductivity type connecting said field-effect transistor and said capacitor of said memory cell is common to said bipolar transistor provided in said semiconductor substrate means.
Claim 5
Dependent Claim
251 words
A semiconductor integrated circuit device as set forth in claim 3, wherein said bipolar transistor provided in said semiconductor substrate means is a vertical bipolar transistor having collector, base and emitter regions; the portion of said semiconductor substrate means of one conductivity type in which said vertical bipolar transistor is disposed having a region of the other conductivity type disposed above the buried semiconductor layer of the other conductivity type and opening onto the top surface of said semiconductor substrate means, said last-mentioned region of the other conductivity type defining the collector region; a region of said one conductivity type disposed in said collector region of the other conductivity type and defining the base region; a region of the other conductivity type disposed in said base region of said one conductivity type and defining the emitter region, said emitter region opening onto the top surface of said semiconductor substrate means; a collector electrode contact region of the other conductivity type and having a higher dopant concentration than the collector region of the other conductivity type disposed in said semiconductor substrate means and opening onto the top surface thereof in spaced relation to said base region and said emitter region disposed therein; and said region of the other conductivity type which connects the field-effect transistor and the capacitor of said memory cell and common to said bipolar transistor connecting said collector electrode contact region of higher dopant concentration of the other conductivity type to said collector region of the other conductivity type.
Claim 6
Dependent Claim
79 words
A semiconductor integrated circuit device as set forth in claim 1, further including a channel stopper region of said one conductivity type of higher dopant concentration than said semiconductor substrate of said one conductivity type disposed below each of said plurality of vertical trenches included in said memory cell portion and said bipolar transistor portion of said semiconductor substrate means within said semiconductor substrate means of said one conductivity type and along the bottom of the respective vertical trench.
Claim 7
Dependent Claim
25 words
A semiconductor integrated circuit device as set forth in claim 1, wherein said one conductivity type is P-type and the other conductivity type is N-type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-03 | 1994-12-03 | 1995-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-03 | 1998-12-03 | 1999-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-03 | 2002-12-03 | 2003-06-04 | $7700.00 | Window Closed / Lapsed |