US4819054A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor IC with dual groove isolation
Assignee: Hitachi Ltd
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Filing: 1987-02-06
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Granted: 1989-04-04
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Expires: 2007-02-06
Abstract
Abstract A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease. The U-shaped grooves can each comprise narrow and deep sub-grooves, with thick oxide films formed on the surfaces of the sub-grooves and a thick oxide film formed on a surface of an area between the sub-grooves, and with wiring formed on the oxide on the area between the sub-grooves.
Inventors
- 👤 Mikinori Kawaji
- 👤 Toshihiko Takakura
- 👤 Akihisa Uchida
- 👤 Shigeo Kuroda
- 👤 Yoichi Tamaki
- 👤 Takeo Shiba
- 👤 Kazuhiko Sagara
- 👤 Masao Kawamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:29
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/40; H10D10/441; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/041; H10W10/10; H10W10/17; H10W10/40; Y; Y10; Y10S; Y10S148/00; Y10S148/05
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
293 words
A semiconductor integrated circuit device having a plurality of active regions in a semiconductor substrate, in which active regions a number of semiconductor elements are formed, and an inactive region in the semiconductor substrate, the inactive region having located thereon wirings, the wirings being connected to at least one of said number of semiconductor elements, with the inactive regions being positioned adjacent one of said plurality of active regions, comprising: (a) the semiconductor substrate, having a main surface; (b) a pair of grooves formed in the semiconductor substrate, each groove of the pair of grooves being formed so as to extend from said main surface into the semiconductor substrate, the pair of grooves defining said inactive region therebetween, the pair of grooves having groove surfaces in the substrate extending from said main surface into the substrate; (c) a single first insulating member formed on the groove surfaces of the pair of grooves, and a second insulating member extending on said semiconductor substrate, on said inactive region, between said pair of grooves, the first insulating member, on the grooves surfaces of the pair of grooves, including a silicon oxide film formed on the groove surfaces and a silicon nitride film formed on the silicon oxide film, and the second insulating member, on the inactive region, including an insulating film of a sufficient thickness for suppressing a parasitic capacitance of said wiring below a predetermined level; (d) a polycrystalline silicon body filling each groove of said pair of grooves such that each of said pair of grooves includes the silicon oxide and silicon nitride films and said body of polycrystalline silicon; and (e) said wirings, located on said inactive regions such that said second insulating member is interposed between the inactive region and the wirings.
Claim 2
Dependent Claim
293 words
A semiconductor integrated circuit device having a plurality of active regions in a semiconductor substrate, in which active regions a number of semiconductor elements are formed, and an inactive region in the semiconductor substrate, the inactive region having located thereon wirings, the wirings being connected to at least one of said number of semiconductor elements, with the inactive regions being positioned adjacent one of said plurality of active regions, comprising: (a) the semiconductor substrate, having a main surface; (b) a pair of grooves formed in the semiconductor substrate, each groove of the pair of grooves being formed so as to extend from said main surface into the semiconductor substrate, the pair of grooves defining said inactive region therebetween, the pair of grooves having groove surfaces in the substrate extending from said main surface into the substrate; (c) a single first insulating member formed on the groove surfaces of the pair of grooves, and a second insulating member extending on said semiconductor substrate, on said inactive region, between said pair of grooves, the first insulating member, on the grooves surfaces of the pair of grooves, including a silicon oxide film formed on the groove surfaces and a silicon nitride film formed on the silicon oxide film, and the second insulating member, on the inactive region, including an insulating film of a sufficient thickness for suppressing a parasitic capacitance of said wiring below a predetermined level; (d) a polycrystalline silicon body filling each groove of said pair of grooves such that each of said pair of grooves includes the silicon oxide and silicon nitride films and said body of polycrystalline silicon; and (e) said wirings, located on said inactive regions such that said second insulating member is interposed between the inactive region and the wirings.
Claim 3
Dependent Claim
17 words
A semiconductor integrated circuit device according to claim 1, wherein the semiconductor substrate is a silicon substrate.
Claim 4
Dependent Claim
25 words
A semiconductor integrated circuit device according to claim 2, further comprising an isolation region formed in at least one of said plurality of active regions.
Claim 5
Dependent Claim
30 words
A semiconductor integrated circuit device according to claim 3, wherein said isolation region includes a silicon oxide layer formed in said at least one of said plurality of active regions.
Claim 6
Dependent Claim
37 words
A semiconductor integrated circuit device according to claim 4, wherein the silicon oxide layer has a thickness substantially the same as that of the first insulating member formed on the groove surface of the pair of grooves.
Claim 7
Dependent Claim
33 words
A semiconductor integrated circuit device according to claim 3, wherein said isolation region is a groove, formed in said at least one of said plurality of active regions, filled with a filling material.
Claim 8
Dependent Claim
275 words
A semiconductor integrated circuit device having a plurality of active regions in a Si substrate, in which active regions a number of semiconductor elements are formed, and an inactive region in the Si substrate, the inactive region having located thereon wirings, the wirings being connected to at least one of said number of semiconductor elements, with the inactive region being positioned adjacent one of said plurality of active regions, comprising: (a) the Si substrate, having a main surface; (b) a pair of grooves formed in the Si substrate, each groove of the pair of grooves being formed so as to extend from said main surface into the Si substrate, the pair of grooves defining the inactive region therebetween, the pair of grooves having groove surfaces in the substrate extending from said main surface into the substrate; (c) a first insulating member formed on surfaces of each groove of said pairs of grooves, and a second insulating member extending on said Si substrate, on said inactive region, between said pair of grooves, said first insulating member including a silicon oxide film adjacent the groove surfaces and a silicon nitride film adjacent the silicon oxide film, the second insulating member including an insulating film of a sufficient thickness for suppressing a parasitic capacitance of said wiring below a predetermined level; (d) a polycrystalline silicon body filling each groove of said pair grooves such that each of said pair grooves includes the silicon oxide and silicon nitride films and said body of polycrystalline silicon; and (e) said wirings, located on said inactive region such that said second insulating member is interposed between the inactive regions and the wirings.
Claim 9
Dependent Claim
275 words
A semiconductor integrated circuit device having a plurality of active regions in a Si substrate, in which active regions a number of semiconductor elements are formed, and an inactive region in the Si substrate, the inactive region having located thereon wirings, the wirings being connected to at least one of said number of semiconductor elements, with the inactive region being positioned adjacent one of said plurality of active regions, comprising: (a) the Si substrate, having a main surface; (b) a pair of grooves formed in the Si substrate, each groove of the pair of grooves being formed so as to extend from said main surface into the Si substrate, the pair of grooves defining the inactive region therebetween, the pair of grooves having groove surfaces in the substrate extending from said main surface into the substrate; (c) a first insulating member formed on surfaces of each groove of said pairs of grooves, and a second insulating member extending on said Si substrate, on said inactive region, between said pair of grooves, said first insulating member including a silicon oxide film adjacent the groove surfaces and a silicon nitride film adjacent the silicon oxide film, the second insulating member including an insulating film of a sufficient thickness for suppressing a parasitic capacitance of said wiring below a predetermined level; (d) a polycrystalline silicon body filling each groove of said pair grooves such that each of said pair grooves includes the silicon oxide and silicon nitride films and said body of polycrystalline silicon; and (e) said wirings, located on said inactive region such that said second insulating member is interposed between the inactive regions and the wirings.
Claim 10
Dependent Claim
22 words
A semiconductor integrated circuit device according to claim 7, further comprising: second and third insulating films formed on said polycrystalline silicon body.
Claim 11
Dependent Claim
57 words
A semiconductor integrated circuit device according to claim 8, wherein said second insulating film is made of silicon oxide and said third insulating film is made of silicon nitride and wherein the thickness of said second insulating film made of silicon oxide is larger than the thickness of the silicon oxide film of the first insulating member.
Claim 12
Dependent Claim
27 words
A semiconductor integrated circuit device according to claim 7, further comprising: second and third insulating films formed on said polycrystalline silicon body and on said inactive region.
Claim 13
Dependent Claim
48 words
A semiconductor integrated circuit device according to claim 10, wherein said second insulating film is made of silicon oxide and said third insulating film is made of silicon nitride and wherein the thickness of said second silicon oxide film is larger than that of said silicon oxide film.
Claim 14
Dependent Claim
17 words
A semiconductor integrated circuit device according to claim 11, wherein said semiconductor integrated circuit device includes MOSFETs.
Claim 15
Dependent Claim
48 words
A semiconductor integrated circuit device according to claim 11, wherein said Si substrate includes a collector buried layer formed on an Si body, wherein said semiconductor integrated circuit device includes bipolar devices, and wherein said pair of grooves extend through said collector buried layer of said silicon substrate.
Claim 16
Dependent Claim
71 words
A semiconductor integrated circuit device according to claim 7, wherein the Si substrate further comprises: a collector buried layer formed in a surface region of a Si body of said Si substrate; and a Si epitaxial layer formed on said collector buried layer, said collector buried layer being cut by said pair of grooves, said pair of grooves extending from a surface of said Si epitaxial layer to said Si body.
Claim 17
Dependent Claim
43 words
A semiconductor integrated circuit device according to claim 7, wherein a further groove, shallower than said pair of grooves, is provided between said pair of grooves, said semiconductor integrated circuit device further comprising a further polycrystalline silicon body filling up said further groove.
Claim 18
Dependent Claim
48 words
A semiconductor integrated circuit device according to claim 7, further comprising an insulating film formed on the surface of at least one of the plurality of the active regions, and wherein said insulating film has a plurality of openings and has a portion thicker than other portions thereof.
Claim 19
Dependent Claim
56 words
A semiconductor integrated circuit device according to claim 16, wherein said member of semiconductor elements include a bipolar transistor provided in said at least one of the plurality of the active regions, and wherein said portion thicker than other portions thereof is provided between a base region and a collector contact region of said bipolar transistor.
Claim 20
Dependent Claim
167 words
Semiconductor substrate, for forming an integrated circuit device, comprising: (a) a semiconductor body having a main surface; (b) a plurality of pairs of grooves formed in said semiconductor body, extending from said surface into said semiconductor body, exposing surfaces of the semiconductor body, each pair, of said plurality of pairs of grooves, having sandwiched therebetween, in the semiconductor body, an inactive region, and with active regions being provided in portions of the semiconductor body other than portions thereof having the inactive regions; (c) a continuous isolation oxide layer, formed on surfaces of the semiconductor body exposed in each of the grooves of the plurality of pairs of grooves, and on said main surface of the semiconductor body in the inactive regions; (d) a silicon nitride layer formed on said isolation oxide layer in each of the grooves of the plurality of pairs of grooves; and (e) a polycrystalline silicon filling up each of the grooves, with a silicon oxide layer formed on top of the polycrystalline silicon.
Claim 21
Dependent Claim
167 words
Semiconductor substrate, for forming an integrated circuit device, comprising: (a) a semiconductor body having a main surface; (b) a plurality of pairs of grooves formed in said semiconductor body, extending from said surface into said semiconductor body, exposing surfaces of the semiconductor body, each pair, of said plurality of pairs of grooves, having sandwiched therebetween, in the semiconductor body, an inactive region, and with active regions being provided in portions of the semiconductor body other than portions thereof having the inactive regions; (c) a continuous isolation oxide layer, formed on surfaces of the semiconductor body exposed in each of the grooves of the plurality of pairs of grooves, and on said main surface of the semiconductor body in the inactive regions; (d) a silicon nitride layer formed on said isolation oxide layer in each of the grooves of the plurality of pairs of grooves; and (e) a polycrystalline silicon filling up each of the grooves, with a silicon oxide layer formed on top of the polycrystalline silicon.
Claim 22
Dependent Claim
27 words
A semiconductor substrate according to claim 18, wherein the semiconductor body is formed of silicon, and the first continuous isolation oxide layer is a silicon oxide layer.
Claim 23
Dependent Claim
211 words
A semiconductor integrated circuit device comprising: (a) a semiconductor body having a main surface; (b) a plurality of pairs of grooves formed in said semiconductor body, extending from said main surface into said semiconductor body, exposing surfaces of the semiconductor body, each pair, of said plurality of pairs of grooves, having sandwiched therebetween, in the semiconductor body, an inactive region, with active regions being provided in portions of the semiconductor body other than portions thereof having the inactive regions; (c) a first isolation oxide film formed on surfaces of the semiconductor body exposed in each of the grooves of the plurality of pairs of grooves, and on said main surface of the semiconductor body in the inactive regions; (d) a silicon nitride layer formed on said first isolation oxide film in each of said grooves; and (e) a second isolation oxide film over a portion of at least one of the active regions so as to define first and second sub-regions of said at least one of the active regions, with the first sub-region being a first conductivity type and the second sub-region being of a second conductivity type opposite to the first conductivity type, the second isolation oxide film constituting an electrical isolation member between the first and second sub-regions.
Claim 24
Dependent Claim
211 words
A semiconductor integrated circuit device comprising: (a) a semiconductor body having a main surface; (b) a plurality of pairs of grooves formed in said semiconductor body, extending from said main surface into said semiconductor body, exposing surfaces of the semiconductor body, each pair, of said plurality of pairs of grooves, having sandwiched therebetween, in the semiconductor body, an inactive region, with active regions being provided in portions of the semiconductor body other than portions thereof having the inactive regions; (c) a first isolation oxide film formed on surfaces of the semiconductor body exposed in each of the grooves of the plurality of pairs of grooves, and on said main surface of the semiconductor body in the inactive regions; (d) a silicon nitride layer formed on said first isolation oxide film in each of said grooves; and (e) a second isolation oxide film over a portion of at least one of the active regions so as to define first and second sub-regions of said at least one of the active regions, with the first sub-region being a first conductivity type and the second sub-region being of a second conductivity type opposite to the first conductivity type, the second isolation oxide film constituting an electrical isolation member between the first and second sub-regions.
Claim 25
Dependent Claim
56 words
A semiconductor integrated circuit device according to claim 20, further comprising a wiring for said integrated circuit device, said wiring being provided over the first isolation oxide film on the inactive regions so that said first isolation oxide film separates the wirings from the semiconductor body to minimize parasitic capacitance between the wirings and semiconductor body.
Claim 26
Dependent Claim
24 words
A semiconductor integrated circuit device according to claim 20, wherein the first and second isolation oxide films are films formed simultaneously with each other.
Claim 27
Dependent Claim
27 words
A semiconductor integrated circuit device according to claim 1, wherein said inactive region is positioned between a pair of active regions of said plurality of active regions.
Claim 28
Dependent Claim
33 words
A semiconductor integrated circuit device according to claim 1, wherein said wirings are disposed on the insulating film of said second insulating member, on said inactive region, and extend along said inactive region.
Claim 29
Dependent Claim
43 words
A semiconductor integrated circuit device according to claim 24, wherein said insulating film of the second insulating member is formed of silicon oxide, and wherein said wirings are disposed directly on the silicon oxide of said insulating film of the second insulating member.
Claim 30
Dependent Claim
48 words
A semiconductor integrated circuit device according to claim 1, wherein said insulating film of said second insulating member, on said inactive region, is a silicon oxide film, of a thickness larger than that of the silicon oxide film formed on the groove surfaces of the pair of grooves.
Claim 31
Dependent Claim
70 words
A semiconductor integrated circuit device according to claim 1, wherein said insulating film of said second insulating member, on the inactive region, includes a silicon oxide sub-film, provided on the inactive region, and a silicon nitride sub-film provided on the silicon oxide sub-film, the total thickness of the silicon oxide and silicon nitride sub-films being sufficient so as to suppress the parasitic capacitance of the wirings below the predetermined level.
Claim 32
Dependent Claim
54 words
A semiconductor integrated circuit device according to claim 8, wherein the second insulating film, of said second and third insulating films, is a silicon oxide film, formed on the polycrystalline silicon body, and the third insulating film is a silicon nitride film, formed on the silicon oxide film formed on the polycrystalline silicon body.
Claim 33
Dependent Claim
43 words
A semiconductor integrated circuit device according to claim 7, wherein the insulating film of said second insulating member is a silicon oxide film, and said wirings are provided directly on the silicon oxide film of the insulating film of the second insulating member.
Claim 34
Dependent Claim
49 words
A semiconductor integrated circuit device according to claim 18, wherein each of the active regions and the inactive regions has an upper surface, corresponding to the main surface of the semiconductor body, the upper surface of each active region and each inactive region being substantially in the same plane.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-03 | 1992-10-03 | 1993-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-03 | 1996-10-03 | 1997-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-03 | 2000-10-03 | 2001-04-04 | $7700.00 | Window Closed / Lapsed |