Method of making a trench capacitor and dram memory cell

Claim 1

A method of fabricating a trench capacitor in an integrated circuit containing a plurality of circuit elements formed in a semiconductor substrate having a substrate conductivity type, comprising the steps of: forming a protective layer on said substrate; cutting an implant aperture having first and second aperture dimensions along first and second axes in said substrate, in a predetermined location in said substrate dimensions along said first and second axes, through said protective layer to said substrate; implanting a predetermined dose of ions of conductivity type opposite to said substrate conductivity type; diffusing said dose of ions into said substrate by heating said substrate to a predetermined temperature for a predetermined time such that a substantial concentration of said ions of said opposite conductivity type extends a predetermined distance from said implant aperture, whereby that portion of said dose of ions extending in said substrate below said predetermined capacitor plate location forms a plate conductive region extending downwardly into said substrate along a third axis and having first, second and third plate dimensions along said first, second and third axes; cutting a trench into said substrate through said implant aperture, thereby forming a trench wall on that surface of said trench extending into said substrate through said plate conductive region with a wall area having a wall length greater than said first plate dimension along said first axis and a wall depth greater than said third plate dimension along said third axis; growing a wall layer of silicon dioxide on said trench wall adjacent said plate conductive region and extending along said trench wall beyond said plate conductive region; filling said trench with polycrystalline silicon filler heavily doped with a trench dopant material of the same conductivity type as said substrate conductivity type and having the capacity of diffusing through thin layers of silicon dioxide; and heating said substrate to a predetermined temperature for a predetermined time sufficient to diffuse a predetermined quantity of said trench dopant material through said wall layer of silicon dioxide to form a diffused channel stop region disposed about said plate conductive region in that portion of said silicon substrate abutting said trench wall and outside said first and third plate dimensions, whereby a parallel-plate capacitor is formed, one plate of which consists of said conductive plate region and the other plate of which is formed by said heavily doped polycrystalline filler, which capcitor has improved resistance to discharge through the effect of said diffused channel stop region.

Claim 2

A method of fabricating a trench capacitor in an integrated circuit containing a plurality of circuit elements formed in a semiconductor substrate having a substrate conductivity type, comprising the steps of: forming a protective layer on said substrate; cutting an implant aperture having first and second aperture dimensions along first and second axes in said substrate, in a predetermined location in said substrate dimensions along said first and second axes, through said protective layer to said substrate; implanting a predetermined dose of ions of conductivity type opposite to said substrate conductivity type; diffusing said dose of ions into said substrate by heating said substrate to a predetermined temperature for a predetermined time such that a substantial concentration of said ions of said opposite conductivity type extends a predetermined distance from said implant aperture, whereby that portion of said dose of ions extending in said substrate below said predetermined capacitor plate location forms a plate conductive region extending downwardly into said substrate along a third axis and having first, second and third plate dimensions along said first, second and third axes; cutting a trench into said substrate through said implant aperture, thereby forming a trench wall on that surface of said trench extending into said substrate through said plate conductive region with a wall area having a wall length greater than said first plate dimension along said first axis and a wall depth greater than said third plate dimension along said third axis; growing a wall layer of silicon dioxide on said trench wall adjacent said plate conductive region and extending along said trench wall beyond said plate conductive region; filling said trench with polycrystalline silicon filler heavily doped with a trench dopant material of the same conductivity type as said substrate conductivity type and having the capacity of diffusing through thin layers of silicon dioxide; and heating said substrate to a predetermined temperature for a predetermined time sufficient to diffuse a predetermined quantity of said trench dopant material through said wall layer of silicon dioxide to form a diffused channel stop region disposed about said plate conductive region in that portion of said silicon substrate abutting said trench wall and outside said first and third plate dimensions, whereby a parallel-plate capacitor is formed, one plate of which consists of said conductive plate region and the other plate of which is formed by said heavily doped polycrystalline filler, which capcitor has improved resistance to discharge through the effect of said diffused channel stop region.