BICMOS latch circuit for latching differential signals

Claim 2

A data latch having differential input terminals for receiving differential input signals from a bus, the data latch comprising: a device having a PN junction coupled to a first reference voltage terminal, wherein the device is for controlling a voltage potential on the differential input terminals and comprises: a first bipolar transistor having a first current electrode coupled to a first power supply terminal, a second current electrode coupled to a first one of the differential input terminals, and a control electrode; a second bipolar transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the other of the differential input terminals, and a control electrode; a third bipolar transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the control electrode of the second bipolar transistor, and a control electrode coupled to the first reference voltage terminal; and a fourth bipolar transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the control electrode of the first bipolar transistor, and a control electrode coupled to the first reference voltage terminal; the data latch further comprising: a current sourcing circuit coupled to the device, wherein the current sourcing circuit controls a current flow in the data latch; and a data storage circuit coupled to the device, the current sourcing circuit, and the differential input terminals, for storing the differential input signals; and wherein, the differential input signals pass from the differential input terminals through the data storage circuit to the bus when an enable signal is in a first state, and the stored differential input signals are provided to the bus by the data latch when the enable signal is in a second state.

Claim 3

The data latch of claim 1 wherein the current sourcing circuit comprises: a first transistor having a first current electrode, a second current electrode, and a control electrode coupled for receiving the enable signal; a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply terminal, and a control electrode coupled to a second reference voltage terminal; a third transistor having a first current electrode, a second current electrode, and a control electrode coupled for receiving the enable signal; and a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a second current electrode coupled to the second power supply terminal, and a control electrode coupled to the second reference voltage terminal.

Claim 4

The data latch of claim 1 wherein the current sourcing circuit receives a biasing signal for controlling an amount of current used by the data storage circuit.

Claim 5

A data latch having differential input terminals for receiving differential input signals from a bus, the data latch comprising: a device having a PN junction coupled to a first reference voltage terminal, wherein the device is for controlling a voltage potential on the differential input terminals; a current sourcing circuit coupled to the device, wherein the current sourcing circuit controls a current flow in the data latch; a data storage circuit coupled to the device, the current sourcing circuit, and the differential input terminals, for storing the differential input signals, the data storage circuit comprising: a first bipolar transistor having a first current electrode coupled to a first power supply terminal, a second current electrode coupled to a first one of the differential input terminals, and a control electrode; a second bipolar transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the other of the differential input terminals, and a control electrode; a third bipolar transistor having a first current electrode coupled to the control electrode of the second bipolar transistor, a control electrode coupled to the first one of the differential input terminals, and a second current electrode; a fourth bipolar transistor having a first current electrode coupled to the control electrode of the first bipolar transistor, a control electrode coupled to the other of the differential input terminals, and a second current electrode coupled to the second current electrode of the third bipolar transistor; a first resistor having a first terminal coupled to the first reference voltage terminal and a second terminal coupled to the control electrode of the first bipolar transistor; a second resistor having a first terminal coupled to the first reference voltage terminal and a second terminal coupled to the control electrode of the second bipolar transistor; a first transistor having a first current electrode coupled to the first one of the differential input terminals, a second current electrode coupled to a second power supply terminal, and a control electrode coupled to a second reference voltage terminal; and a second transistor having a first current electrode coupled to the other of the differential input terminals, a second current electrode coupled to the second power supply terminal, and a control electrode coupled to the second reference voltage terminal.

Claim 6

A data latch having differential input terminals for receiving differential input signals from a bus, the data latch comprising: a device having a PN junction coupled to a first reference voltage terminal, wherein the device is for controlling a voltage potential on the differential input terminals; a current sourcing circuit coupled to the device, wherein the current sourcing circuit controls a current flow in the data latch; a data storage circuit coupled to the device, the current sourcing circuit, and the differential input terminals, for storing the differential input signals, the data storage circuit comprising: a first bipolar transistor having a first current electrode coupled to a first power supply terminal, a second current electrode coupled to a first one of the differential input terminals, and a control electrode; a second bipolar transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the other of the differential input terminals, and a control electrode; a third bipolar transistor having a first current electrode coupled to the control electrode of the second bipolar transistor, a control electrode coupled to the first one of the differential input terminals, and a second current electrode; a fourth bipolar transistor having a first current electrode coupled to the control electrode of the first bipolar transistor, a control electrode coupled to the other of the differential input terminals, and a second current electrode coupled to the second current electrode of the third bipolar transistor; a first resistor having a first terminal coupled to the first reference voltage terminal and a second terminal coupled to the control electrode of the first bipolar transistor; a second resistor having a first terminal coupled to the first reference voltage terminal and a second terminal coupled to the control electrode of the second bipolar transistor; a first transistor having a first current electrode coupled to the first one of the differential input terminals, a second current electrode coupled to a second power supply terminal, and a control electrode coupled to a second reference voltage terminal; and a second transistor having a first current electrode coupled to the other of the differential input terminals, a second current electrode coupled to the second power supply terminal, and a control electrode coupled to the second reference voltage terminal.

Claim 7

The data latch of claim 4 wherein the data storage circuit comprises a third transistor having a first current electrode coupled to the second current electrode of the third bipolar transistor and to the second current electrode of the fourth bipolar transistor, a second current electrode coupled to the second power supply terminal, and a control electrode coupled to the second reference voltage terminal.

Claim 8

The data latch of claim 4 further comprising: a fifth bipolar transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the control electrode of the second bipolar transistor, and the control electrode coupled to a first reference voltage terminal; and a sixth bipolar transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the control electrode of the first bipolar transistor, and a control electrode coupled to the first reference voltage terminal.

Claim 9

The data latch of claim 4, wherein the first transistor and the second transistor are metal-oxide semiconductor transistors.

Claim 10

A latch for storing a data value from a bus, and for receiving a first reference voltage signal, a second reference voltage signal, and an enable signal, wherein the enable signal, when in a first state, disables the latch so that the latch is not providing the data value to the bus and the enable signal, when in a second state, enables the latch so that the data value is stored in the latch and provides the stored data value to the bus, and the latch comprises a diode clamping circuit comprising: a first bipolar transistor having a first current electrode coupled to a first power supply terminal, a second current electrode, and a control electrode for receiving the first reference voltage signal; and a second bipolar transistor having a first current electrode coupled to the first power supply terminal, a second current electrode, and a control electrode coupled to the control electrode of the first bipolar transistor.

Claim 11

A latch for storing a data value from a bus, and for receiving a first reference voltage signal, a second reference voltage signal, and an enable signal, wherein the enable signal, when in a first state, disables the latch so that the latch is not providing the data value to the bus and the enable signal, when in a second state, enables the latch so that the data value is stored in the latch and provides the stored data value to the bus, and the latch comprises a diode clamping circuit comprising: a first bipolar transistor having a first current electrode coupled to a first power supply terminal, a second current electrode, and a control electrode for receiving the first reference voltage signal; and a second bipolar transistor having a first current electrode coupled to the first power supply terminal, a second current electrode, and a control electrode coupled to the control electrode of the first bipolar transistor.

Claim 12

A latch, having differential input terminals, for storing a data value from a bus, and for receiving a first reference voltage signal, a second reference voltage signal, and an enable signal, wherein the enable signal, when in a first state, disables the latch so that the latch is not providing the data value to the bus and the enable signal, when in a second state, enables the latch so that the data value is stored in the latch and provides the stored data value to the bus, wherein the latch comprises a data storage circuit which includes: a first bipolar transistor having a first current electrode coupled to a first power supply terminal, a second current electrode coupled to a first one of the differential input terminals, and a control electrode; a second bipolar transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the other of the differential input terminals, and a control electrode; a third bipolar transistor having a first current electrode coupled to the control electrode of the second bipolar transistor, a control electrode coupled to the first one of the differential input terminals, and a second current electrode; a fourth bipolar transistor having a first current electrode coupled to the control electrode of the first bipolar transistor, a control electrode coupled to the other of the differential input terminals, and a second current electrode coupled to the second current electrode of the third bipolar transistor; a first resistor having a first terminal coupled to receive the first reference voltage signal and a second terminal coupled to the control electrode of the first bipolar transistor; a second resistor having a first terminal coupled to receive the first reference voltage signal and a second terminal coupled to the control electrode of the second bipolar transistor; a first transistor having a first current electrode coupled to the first one of the differential input terminals, a second current electrode coupled to a second power supply terminal, and a control electrode coupled to receive the second reference voltage signal; and a second transistor having a first current electrode coupled to the other of the differential input terminals, a second current electrode coupled to the second power supply terminal, and a control electrode coupled to the second reference voltage signal.

Claim 13

A latch, having differential input terminals, for storing a data value from a bus, and for receiving a first reference voltage signal, a second reference voltage signal, and an enable signal, wherein the enable signal, when in a first state, disables the latch so that the latch is not providing the data value to the bus and the enable signal, when in a second state, enables the latch so that the data value is stored in the latch and provides the stored data value to the bus, wherein the latch comprises a data storage circuit which includes: a first bipolar transistor having a first current electrode coupled to a first power supply terminal, a second current electrode coupled to a first one of the differential input terminals, and a control electrode; a second bipolar transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the other of the differential input terminals, and a control electrode; a third bipolar transistor having a first current electrode coupled to the control electrode of the second bipolar transistor, a control electrode coupled to the first one of the differential input terminals, and a second current electrode; a fourth bipolar transistor having a first current electrode coupled to the control electrode of the first bipolar transistor, a control electrode coupled to the other of the differential input terminals, and a second current electrode coupled to the second current electrode of the third bipolar transistor; a first resistor having a first terminal coupled to receive the first reference voltage signal and a second terminal coupled to the control electrode of the first bipolar transistor; a second resistor having a first terminal coupled to receive the first reference voltage signal and a second terminal coupled to the control electrode of the second bipolar transistor; a first transistor having a first current electrode coupled to the first one of the differential input terminals, a second current electrode coupled to a second power supply terminal, and a control electrode coupled to receive the second reference voltage signal; and a second transistor having a first current electrode coupled to the other of the differential input terminals, a second current electrode coupled to the second power supply terminal, and a control electrode coupled to the second reference voltage signal.

Claim 14

The data latch of claim 9, wherein the first transistor and the second transistor are metal-oxide semiconductor transistors.