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US5576572A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor integrated circuit device and method of manufacturing the same

Assignee: Toshiba Corp
•
Filing: 1994-04-29
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Granted: 1996-11-19
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Expires: 2014-04-29
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Abstract

Abstract A semiconductor integrated circuit device having a bipolar transistor and contact in the form of a wired layer by using different impurities for doping the emitter electrode and the wired layer of the device, both of which are made of polysilicon. The emitter electrode, formed on an emitter region of a p-type silicon semiconductor substrate, is doped with an n-type impurity having a low diffusion coefficient. A polysilicon wired layer, formed on an impurity diffusion region in an active region of the semiconductor substrate, is doped with another impurity that can effectively destroy native oxide films. With such an arrangement of selectively using impurities, the temperature of thermally treating the emitter region can be less than 850° C.

Inventors

  • 👤 Takeo Maeda
  • 👤 Hiroshi Gojohbori

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 01:45
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/15; H10B10/18; H10B12/00; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/714; H10D64/00; H10D64/20; H10D64/23; H10D64/231; H10D84/00; H10D84/40; H10D84/401

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 169 words
A semiconductor integrated circuit device comprising: a semiconductor substrate; a bipolar transistor formed on said substrate and including an emitter region; a MOS transistor formed on said semiconductor substrate and including n-type source and drain regions; an emitter electrode formed on the emitter region of said bipolar transistor and made of polysilicon doped with a first n-type impurity having a small diffusion coefficient; a polysilicon wired layer formed on one of said n-type source and drain regions and doped with a second n-type impurity, said second n-type impurity removing undesired native oxide films on the semiconductor substrate, said polysilicon wired layer being doped with the second n-type impurity to the exclusion of the first n-type impurity; a high melting-point metal film formed on the surface of said emitter electrode and said polysilicon wired layer, said film being a silicide film selected from the group consisting of tungsten silicide, molybdenum silicide, titanium silicide and tantalum silicide; and a barrier metal disposed between said silicide film and said polysilicon wired layer.
Claim 2
Dependent Claim 169 words
A semiconductor integrated circuit device comprising: a semiconductor substrate; a bipolar transistor formed on said substrate and including an emitter region; a MOS transistor formed on said semiconductor substrate and including n-type source and drain regions; an emitter electrode formed on the emitter region of said bipolar transistor and made of polysilicon doped with a first n-type impurity having a small diffusion coefficient; a polysilicon wired layer formed on one of said n-type source and drain regions and doped with a second n-type impurity, said second n-type impurity removing undesired native oxide films on the semiconductor substrate, said polysilicon wired layer being doped with the second n-type impurity to the exclusion of the first n-type impurity; a high melting-point metal film formed on the surface of said emitter electrode and said polysilicon wired layer, said film being a silicide film selected from the group consisting of tungsten silicide, molybdenum silicide, titanium silicide and tantalum silicide; and a barrier metal disposed between said silicide film and said polysilicon wired layer.
Claim 3
Dependent Claim 168 words
A semiconductor integrated circuit device comprising: a semiconductor substrate; a bipolar transistor formed on said substrate and including an emitter region; a MOS transistor formed on said semiconductor substrate and including n-type source and drain regions; an emitter electrode formed on the emitter region of said bipolar transistor and made of polysilicon doped with a first n-type impurity having a small diffusion coefficient; a polysilicon wired layer formed on one of said n-type source and drain regions and doped with a second n-type impurity, said second n-type impurity removing undesired native oxide films on the semiconductor substrate, said polysilicon wired layer being doped with the second n-type impurity to the exclusion of the first n-type impurity; a high melting-point metal film formed on the surface of said emitter electrode and said polysilicon wired layer, said film being a silicide film selected from the group consisting of tungsten silicide, molybdenum silicide, titanium silicide and tantalum silicide; and a barrier metal disposed between said silicide film and said emitter electrode.
Claim 4
Dependent Claim 168 words
A semiconductor integrated circuit device comprising: a semiconductor substrate; a bipolar transistor formed on said substrate and including an emitter region; a MOS transistor formed on said semiconductor substrate and including n-type source and drain regions; an emitter electrode formed on the emitter region of said bipolar transistor and made of polysilicon doped with a first n-type impurity having a small diffusion coefficient; a polysilicon wired layer formed on one of said n-type source and drain regions and doped with a second n-type impurity, said second n-type impurity removing undesired native oxide films on the semiconductor substrate, said polysilicon wired layer being doped with the second n-type impurity to the exclusion of the first n-type impurity; a high melting-point metal film formed on the surface of said emitter electrode and said polysilicon wired layer, said film being a silicide film selected from the group consisting of tungsten silicide, molybdenum silicide, titanium silicide and tantalum silicide; and a barrier metal disposed between said silicide film and said emitter electrode.
Claim 5
Dependent Claim 117 words
A semiconductor integrated circuit device comprising: a semiconductor substrate; a bipolar transistor formed on said substrate and including an emitter region; a MOS transistor formed on said semiconductor substrate and including n-type source and drain regions; an emitter electrode formed on the emitter region of said bipolar transistor and made of polysilicon doped with a first n-type impurity having a small diffusion coefficient; and a polysilicon wired layer formed on one of said n-type source and drain regions and doped with a second n-type impurity, said second n-type impurity removing undesired native oxide films on the semiconductor substrate, said polysilicon wired layer being doped with the second n-type impurity to the exclusion of the first n-type impurity.
Claim 6
Dependent Claim 117 words
A semiconductor integrated circuit device comprising: a semiconductor substrate; a bipolar transistor formed on said substrate and including an emitter region; a MOS transistor formed on said semiconductor substrate and including n-type source and drain regions; an emitter electrode formed on the emitter region of said bipolar transistor and made of polysilicon doped with a first n-type impurity having a small diffusion coefficient; and a polysilicon wired layer formed on one of said n-type source and drain regions and doped with a second n-type impurity, said second n-type impurity removing undesired native oxide films on the semiconductor substrate, said polysilicon wired layer being doped with the second n-type impurity to the exclusion of the first n-type impurity.
Claim 7
Dependent Claim 16 words
A semiconductor integrated circuit device according to claim 3, wherein said second n-type impurity is phosphorus.
Claim 8
Dependent Claim 29 words
A semiconductor integrated circuit device according to claim 3, wherein high melting-point metal silicide film is formed on the surface of said emitter electrode and said polysilicon wired layer.
Claim 9
Dependent Claim 25 words
A semiconductor integrated circuit device according to claim 5, wherein said silicide film is one of tungsten silicide, molybdenum silicide, titanium silicide and tantalum silicide.
Claim 10
Dependent Claim 21 words
A semiconductor integrated circuit device according to claim 3, wherein said first n-type impurity having a small diffusion coefficient is As.
Claim 11
Dependent Claim 21 words
A semiconductor integrated circuit device according to claim 3, wherein said first n-type impurity having a small diffusion coefficient is Sb.
Claim 12
Dependent Claim 100 words
A semiconductor integrated circuit device comprising: a semiconductor substrate; a bipolar transistor formed on said substrate and including an emitter region; a MOS transistor formed on said semiconductor substrate and including n-type source and drain regions; an emitter electrode formed on the emitter region of said bipolar transistor and made of polysilicon doped with only a first n-type impurity having a small diffusion coefficient; and a polysilicon wired layer formed on one of said n-type source and drain regions and doped with only a second n-type impurity, said second n-type impurity removing undesired native oxide films on the semiconductor substrate.
Claim 13
Dependent Claim 100 words
A semiconductor integrated circuit device comprising: a semiconductor substrate; a bipolar transistor formed on said substrate and including an emitter region; a MOS transistor formed on said semiconductor substrate and including n-type source and drain regions; an emitter electrode formed on the emitter region of said bipolar transistor and made of polysilicon doped with only a first n-type impurity having a small diffusion coefficient; and a polysilicon wired layer formed on one of said n-type source and drain regions and doped with only a second n-type impurity, said second n-type impurity removing undesired native oxide films on the semiconductor substrate.

References Cited (Backward Citations)

US5001081A Cited
JPH01196142A Cited
US5089433A Cited
US5221853A Cited
US5150184A Cited
US5091760A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-11-19 2000-05-20 2000-11-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-11-19 2004-05-20 2004-11-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-11-19 2008-05-20 2008-11-19 $7700.00 Window Closed / Lapsed

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