Highly sensitive high performance sense amplifiers

Claim 2

A sense amplifier comprising; first and second nodes, input/output means coupled to said nodes, a pair of cross-coupled bipolar transistors arranged as a regenerative latch coupled at their control electrodes between said nodes, a pair of cross-coupled field effect transistors arranged as regenerative latch coupled at their control electrodes between said nodes, and means for coupling a supply voltage to said transistors.

Claim 3

A sense amplifier as set forth in claim 1 further including first and second impedance means, said first impedance means being connected between the control terminal of one of said bipolar transistors and the control terminal of one of said field effect transistors and said second impedance means being connected between the control terminal of the other of said bipolar transistors and the control terminal of the other of said field effect transistors.

Claim 4

A sense amplifier as set forth in claim 2 wherein each of said impedance means includes a capacitor.

Claim 5

A sense amplifier as set forth in claim 3 further including a first additional field effect transistor connected between the base of said one bipolar transistor and one of said first and second nodes and a second additional field effect transistor connected between the base of said other bipolar transistor and the other of said first and second nodes, said first and second additional transistors being controlled by a clock pulse.

Claim 6

A sense amplifier as set forth in claim 3 further including means coupled to the emitters of said bipolar transistors for compensating for base-emitter mismatch of said pair of bipolar transistors by producing voltage differences across said capacitors.

Claim 7

A sense amplifier as set forth in claim 5 wherein said compensating means includes means for decreasing the voltage at the emitters of said bipolar transistors.

Claim 8

A sense amplifier as set forth in claim 2 wherein said first impedance means includes a first P channel field effect transistor connected between said first node and the base of one of said pair of bipolar transistors and said second impedance means includes a second P channel field effect transistor connected between said second node and the base of the other of said pair of bipolar transistors, the control gates of said first and second P channel transistors being connected to a clock pulse terminal.

Claim 9

A sense amplifier as set forth in claim 1 wherein each of said field effect transistors is a P channel transistor.

Claim 10

A sense amplifier as set forth in claim 1 further including means for precharging said first and second nodes to a common potential during a first period of time and means for applying signals to said nodes during a second period of time.

Claim 11

A sense amplifier as set forth in claim 9 wherein said precharging means includes a voltage equalizing transistor connected between said first and second nodes.

Claim 12

A sense amplifier as set forth in claim 9 wherein said precharging means includes first and second P channel transistors connected to said first and second nodes, respectively.

Claim 13

A sense amplifier as set forth in claim 11 wherein said precharging means further includes a third P channel transistor connected between said first and second nodes and means for turning off said third transistor at a slower rate than the turn off rate of said first and second transistors.

Claim 14

A sense amplifier as set forth in claim 1 wherein said bipolar transistors are NPN transistors and said field effect transistors are P channel transistors.

Claim 15

A sense amplifier as set forth in claim 1 further including means for activating said bipolar transistors during a first period of time and means for activating said field effect transistors during a second period of time.

Claim 16

A sensing circuit comprising; first and second nodes, means for charging said nodes to a common voltage during a first period of time, a first clock pulse terminal, a first bipolar transistor connected between said first node and said first terminal, a second bipolar transistor connected between said second node and said first terminal, a first capacitor connected between said first node and the base of said second bipolar transistor, a second capacitor connected between said second node and the base of said first bipolar transistor, a second clock pulse terminal, a first P channel field effect transistor connected between said first node and said second terminal, the control gate of said first P channel transistor being connected to said second node, a second P channel field effect transistor connected between said second node and said second terminal, the control gate of said second P channel transistor being connected to said first node, and third and fourth P channel field effect transistors connected across said first and second capacitors, respectively, the control gates of said third and fourth P channel transistors being connected to said second terminal.

Claim 17

A sensing circuit comprising; first and second nodes, means for charging said nodes to a common voltage during a first period of time, a first clock pulse terminal, a first bipolar transistor connected between said first node and said first terminal, a second bipolar transistor connected between said second node and said first terminal, a first capacitor connected between said first node and the base of said second bipolar transistor, a second capacitor connected between said second node and the base of said first bipolar transistor, a second clock pulse terminal, a first P channel field effect transistor connected between said first node and said second terminal, the control gate of said first P channel transistor being connected to said second node, a second P channel field effect transistor connected between said second node and said second terminal, the control gate of said second P channel transistor being connected to said first node, and third and fourth P channel field effect transistors connected across said first and second capacitors, respectively, the control gates of said third and fourth P channel transistors being connected to said second terminal.

Claim 18

A sensing circuit as set forth in claim 15 wherein said bipolar transistors are NPN transistors.

Claim 19

A sensing circuit as set forth in claim 15 wherein the collector and emitter of said first bipolar transistor are connected to said first node and said first clock pulse terminal, respectively, and the collector and emitter of said second bipolar transistor are connected to said second node and said first clock pulse terminal, respectively.

Claim 20

A sensing circuit as set forth in claim 15 wherein the collector and emitter of said first bipolar transistor are connected to said first clock pulse terminal and said first node, respectively, and the collector and emitter of said second bipolar transistor are connected to said first clock pulse terminal and said second node, respectively.

Claim 21

A sensing circuit comprising; first and second nodes, means for charging said nodes to a common voltage, a first clock pulse terminal, a first bipolar transistor connected between said first node and said first terminal, a second bipolar transistor connected between said second node and said first terminal, a first capacitor connected between said first node and the base of said second bipolar transistor, a second capacitor connected between said second node and the base of said first bipolar transistor, a supply voltage terminal, a first P channel field effect transistor connected between said first node and said supply voltage terminal, the control gate of said first P channel transistor being connected to said second node, a second P channel field effect transistor connected between said second node and said supply voltage terminal, the control gate of said second P channel transistor being connected to said first node, a second clock pulse terminal, a third P channel field effect transistor connected between said first node and the base of said first bipolar transistor, the control gate of said third P channel transistor being connected to said second terminal, and a fourth P channel field effect transistor connected between said second node and the base of said second bipolar transistor, the control gate of said fourth P channel transistor being connected to said second terminal.

Claim 22

A sensing circuit comprising; first and second nodes, means for charging said nodes to a common voltage, a first clock pulse terminal, a first bipolar transistor connected between said first node and said first terminal, a second bipolar transistor connected between said second node and said first terminal, a first capacitor connected between said first node and the base of said second bipolar transistor, a second capacitor connected between said second node and the base of said first bipolar transistor, a supply voltage terminal, a first P channel field effect transistor connected between said first node and said supply voltage terminal, the control gate of said first P channel transistor being connected to said second node, a second P channel field effect transistor connected between said second node and said supply voltage terminal, the control gate of said second P channel transistor being connected to said first node, a second clock pulse terminal, a third P channel field effect transistor connected between said first node and the base of said first bipolar transistor, the control gate of said third P channel transistor being connected to said second terminal, and a fourth P channel field effect transistor connected between said second node and the base of said second bipolar transistor, the control gate of said fourth P channel transistor being connected to said second terminal.

Claim 23

A sensing circuit as set forth in claim 19 wherein said bipolar transistors are NPN transistors.

Claim 24

A sensing circuit as set forth in claim 19 further including a clock pulse circuit connected to said first clock pulse terminal, said clock pulse circuit including a third capacitor, means for discharging said third capacitor, means for selectively connecting said third capacitor to said first clock pulse terminal, means for selectively connecting said supply voltage terminal to said first clock pulse terminal and means for selectively connecting said first clock pulse terminal to a point of reference potential.

Claim 25

A sensing circuit as set forth in claim 19 wherein the collector and emitter of said first bipolar transistor are connected to said first node and said first clock pulse terminal, respectively, and the collector and emitter of said second bipolar transistor are connected to said second node and said first clock pulse terminal, respectively.

Claim 26

A sensing circuit as set forth in claim 19 wherein the collector and emitter of said first bipolar transistor are connected to said first clock pulse terminal and said first node, respectively, and the collector and emitter of said second bipolar transistor are connected to said first clock pulse terminal and said second node, respectively.