US4494020A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High sensitivity sense amplifier using different threshold valued MOS devices
Assignee: Toshiba Corp
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Filing: 1983-04-13
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Granted: 1985-01-15
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Expires: 2003-04-13
Abstract
Abstract A sense amplifier wherein each of a first through a fourth inverter comprises a driving transistor and a load transistor; the first, second, third and fourth inverters are interconnected in such a way that the outputs of the first and second inverters are applied to the third and fourth inverters, respectively; the first and second inverters have input terminals while the third and fourth inverters have output terminals; one terminal of each of the first through fourth inverters is connected to first power supply while the other terminals of the first and second inverters are connected directly or through a control transistor to second power supply; and the outputs from the first and second inverters are applied to the other terminals of third and fourth inverter, respectively.
Inventors
- 👤 Satoshi Konishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:31
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
336 words
A sense amplifier comprising: (a) a first inverter comprising a series circuit of a first transistor which is a driving transistor and which has a first input terminal and a second transistor which is a load transistor; (b) a second inverter comprising a series circuit of a third transistor which is a driving transistor and which has a second input terminal and a fourth transistor which is a load transistor; (c) a third inverter comprising a series circuit of a fifth transistor which is a driving transistor and to which is applied as an input the output of said second inverter and a sixth transistor which is a load transistor, the junction between said fifth and sixth transistor being a first output terminal; (d) a fourth inverter comprising a series circuit of a seventh transistor which is a driving transistor and to which is applied as an input the output of said first inverter and an eighth transistor which is a load transistor, the junction between said seventh and eighth transistor being a second output terminal; (e) each of said load transistors of said first through fourth inverters having a terminal connected to a first power supply means; (f) said first and third transistors in said first and second inverters having terminals connected to a second power supply means; (g) said fifth transistor in said third inverter having a terminal to which is applied as a power supply the output from said first inverter while said seventh transistor in said fourth inverter having a terminal to which is applied as a power supply the output from said second inverter; (h) said first and third transistors having a first threshold voltage, said second and fourth transistors having a second threshold voltage, said fifth and seventh transistors having a third threshold voltage, and said sixth and eighth transistors having a fourth threshold voltage; and external input signals being applied to said first and second input terminals whereby output signals are derived from said first and second output terminals.
Claim 2
Dependent Claim
336 words
A sense amplifier comprising: (a) a first inverter comprising a series circuit of a first transistor which is a driving transistor and which has a first input terminal and a second transistor which is a load transistor; (b) a second inverter comprising a series circuit of a third transistor which is a driving transistor and which has a second input terminal and a fourth transistor which is a load transistor; (c) a third inverter comprising a series circuit of a fifth transistor which is a driving transistor and to which is applied as an input the output of said second inverter and a sixth transistor which is a load transistor, the junction between said fifth and sixth transistor being a first output terminal; (d) a fourth inverter comprising a series circuit of a seventh transistor which is a driving transistor and to which is applied as an input the output of said first inverter and an eighth transistor which is a load transistor, the junction between said seventh and eighth transistor being a second output terminal; (e) each of said load transistors of said first through fourth inverters having a terminal connected to a first power supply means; (f) said first and third transistors in said first and second inverters having terminals connected to a second power supply means; (g) said fifth transistor in said third inverter having a terminal to which is applied as a power supply the output from said first inverter while said seventh transistor in said fourth inverter having a terminal to which is applied as a power supply the output from said second inverter; (h) said first and third transistors having a first threshold voltage, said second and fourth transistors having a second threshold voltage, said fifth and seventh transistors having a third threshold voltage, and said sixth and eighth transistors having a fourth threshold voltage; and external input signals being applied to said first and second input terminals whereby output signals are derived from said first and second output terminals.
Claim 3
Dependent Claim
74 words
A sense amplifier as set forth in claim 1 wherein: the absolute value of said third threshold voltage is less than or equal to the absolute voltage of said first threshold voltage, the absolute value of said fourth threshold voltage is greater than the absolute value of said first threshold voltage, and the absolute value of said second threshold voltage is less than or equal to the absolute value of said fourth threshold voltage.
Claim 4
Dependent Claim
351 words
A sense amplifier comprising: (a) a first inverter comprising a series circuit of a first transistor which is a driving transistor and which has a first input terminal, and a second transistor which is a load transistor; (b) a second inverter comprising a series circuit of a third transistor which is a driving transistor and which has a second input terminal and a fourth transistor which is a load transistor; (c) a third inverter comprising a series circuit of a fifth transistor which is a driving transistor and to which is applied as an input the output of said second inverter and a sixth transistor which is a load transistor, the junction between said fifth and sixth transistor being a first output terminal; (d) a fourth inverter comprising a series circuit of a seventh transistor which is a driving transistor and to which is applied as an input the output of said first inverter and an eighth transistor which is a load transistor, the junction between said seventh and eighth transistor being a second output terminal; (e) each load transistor of each inverter having a terminal connected to a first power supply; (f) said first and third transistors in said first and second inverters having a common terminal which is connected to a second power supply through a ninth transistor which responds to an external signal; (g) said fifth transistor in said third inverter having a terminal to which is applied as a power supply the output from said first inverter while the seventh transistor in said fourth inverter having a terminal to which is applied as a power supply the output from said second inverter; (h) said first and third transistors having a first threshold voltage, said second and fourth transistors having a second threshold voltage, said fifth and seventh transistors having a third threshold voltage, said sixth and eighth transistors having a fourth threshold voltage and said ninth transistor having a fifth threshold voltage; and external input signals being applied to said first and second input terminals whereby output signals are derived from said first and second output terminals.
Claim 5
Dependent Claim
351 words
A sense amplifier comprising: (a) a first inverter comprising a series circuit of a first transistor which is a driving transistor and which has a first input terminal, and a second transistor which is a load transistor; (b) a second inverter comprising a series circuit of a third transistor which is a driving transistor and which has a second input terminal and a fourth transistor which is a load transistor; (c) a third inverter comprising a series circuit of a fifth transistor which is a driving transistor and to which is applied as an input the output of said second inverter and a sixth transistor which is a load transistor, the junction between said fifth and sixth transistor being a first output terminal; (d) a fourth inverter comprising a series circuit of a seventh transistor which is a driving transistor and to which is applied as an input the output of said first inverter and an eighth transistor which is a load transistor, the junction between said seventh and eighth transistor being a second output terminal; (e) each load transistor of each inverter having a terminal connected to a first power supply; (f) said first and third transistors in said first and second inverters having a common terminal which is connected to a second power supply through a ninth transistor which responds to an external signal; (g) said fifth transistor in said third inverter having a terminal to which is applied as a power supply the output from said first inverter while the seventh transistor in said fourth inverter having a terminal to which is applied as a power supply the output from said second inverter; (h) said first and third transistors having a first threshold voltage, said second and fourth transistors having a second threshold voltage, said fifth and seventh transistors having a third threshold voltage, said sixth and eighth transistors having a fourth threshold voltage and said ninth transistor having a fifth threshold voltage; and external input signals being applied to said first and second input terminals whereby output signals are derived from said first and second output terminals.
Claim 6
Dependent Claim
74 words
A sense amplifier as set forth in claim 3 wherein the absolute value of said third threshold voltage is less than or equal to the absolute value of said first threshold voltage, the absolute value of said fourth threshold voltage being greater than the absolute value of said first threshold voltage and the absolute value of said second threshold voltage being less than or equal to the absolute value of said fourth threshold voltage.
Claim 7
Dependent Claim
29 words
A senes amplifier as set forth in claim 4 wherein the absolute value of said fifth threshold voltage is equal to the absolute value of said first threshold voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-15 | 1988-07-16 | 1989-01-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-15 | 1992-07-16 | 1993-01-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-15 | 1996-07-16 | 1997-01-15 | $7700.00 | Window Closed / Lapsed |