US5239506A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Latch and data out driver for memory arrays
Assignee: International Business Machines Corp
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Filing: 1991-02-04
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Granted: 1993-08-24
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Expires: 2011-02-04
Abstract
Abstract A latch and driver circuit is disclosed for use in reading out data from a random access memory cell. The invention, which may be implemented in BICMOS technology, accomplishes high-speed asynchronous latching, level translation and output driving operations. The invention includes a latch and at least one output driver coupled in parallel to a latch driver.
Inventors
- 👤 William R. Dachtera
- 👤 Leonard C. Ritchie
- 👤 Arthur D. Tuminaro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 12:04
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C7/106
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
42 words
A latch and drive circuit comprising: differential sense amplifier; a BICMOS cross-coupled latch driver coupled to the sense amplifier; a latch coupled to the latch driver; and at least one output driver coupled to the latch driver in parallel with the latch.
Claim 2
Dependent Claim
42 words
A latch and drive circuit comprising: differential sense amplifier; a BICMOS cross-coupled latch driver coupled to the sense amplifier; a latch coupled to the latch driver; and at least one output driver coupled to the latch driver in parallel with the latch.
Claim 3
Dependent Claim
17 words
The circuit of claim 1 in which the sense amplifier comprises a bipolar differential sense amplifier circuit.
Claim 4
Dependent Claim
79 words
A memory comprising: at least one memory cell coupled to two bit lines; a differential sense amplifier circuit coupled to the bit lines for sensing a data bit in the cell; a cross-coupled latch driver circuit coupled to outputs of the sense amplifier circuit; a cross-coupled latch coupled to outputs of the latch driver circuit; and first and second output driver circuits, each coupled in parallel to outputs of the latch driver circuit and to outputs of the latch.
Claim 5
Dependent Claim
79 words
A memory comprising: at least one memory cell coupled to two bit lines; a differential sense amplifier circuit coupled to the bit lines for sensing a data bit in the cell; a cross-coupled latch driver circuit coupled to outputs of the sense amplifier circuit; a cross-coupled latch coupled to outputs of the latch driver circuit; and first and second output driver circuits, each coupled in parallel to outputs of the latch driver circuit and to outputs of the latch.
Claim 6
Dependent Claim
31 words
The circuit of claim 3 in which the latch driver circuit and the output driver circuits each comprise a BICMOS circuit, and the differential sense amplifier circuit comprises a bipolar circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-23 | 1997-02-22 | 1997-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-23 | 2001-02-22 | 2001-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-23 | 2005-02-22 | 2005-08-24 | $7700.00 | Window Closed / Lapsed |