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US6480954B2
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Method of time multiplexing a programmable logic device
Assignee: Xilinx Inc
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Filing: 2001-06-06
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Granted: 2002-11-12
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Expires: 2021-06-06
Abstract
Abstract A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.
Inventors
- 👤 Stephen M. Trimberger
- 👤 Richard A. Carberry
- 👤 Robert Anders Johnson
- 👤 Jennifer Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:04
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17752; G; G06; G06F; G06F30/00; G06F30/30; G06F30/34; H03K19/17756; H03K19/17758; H03K19/1776
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
89 words
A method of simulating a logic network having multiple clocks, the method comprising the steps of: identifying one or more combinational logic elements in the logic network having input signals that do not derive from sequential logic elements controlled by a single clock signal; and re-timing each of the one or more combinational logic elements forward through one or more sequential logic elements, such that each of the one or more combinational logic elements has input signals that derive from sequential logic elements controlled by a single clock signal.
Claim 2
Independent Claim
89 words
A method of simulating a logic network having multiple clocks, the method comprising the steps of: identifying one or more combinational logic elements in the logic network having input signals that do not derive from sequential logic elements controlled by a single clock signal; and re-timing each of the one or more combinational logic elements forward through one or more sequential logic elements, such that each of the one or more combinational logic elements has input signals that derive from sequential logic elements controlled by a single clock signal.
Claim 3
Dependent Claim
34 words
The method of claim 1 , further comprising the step of partitioning the logic network into a plurality of sub-networks, wherein each of the sub-networks operates only in response to a single clock signal.
Claim 4
Dependent Claim
29 words
The method of claim 2 , further comprising the steps of: dividing the sub-networks into a plurality of micro-cycles; and sequencing the micro-cycles in response to a sequencer clock.
Claim 5
Dependent Claim
19 words
The method of claim 3 , further comprising the step of bypassing an idle state while sequencing the micro-cycles.
Claim 6
Dependent Claim
31 words
The method of claim 4 , wherein the bypassing step comprises the step of determining a next micro-cycle to be processed while a last micro-cycle of a sequence is being processed.
Claim 7
Dependent Claim
51 words
The method of claim 2 , further comprising the steps of: dividing the sub-networks into a plurality of micro cycles; and storing a plurality of intermediate logic states corresponding to said plurality of micro cycles, wherein each intermediate logic state is selectively accessible during each of said plurality of micro cycles.
Claim 8
Dependent Claim
53 words
The method of claim 2 , wherein the step of partitioning further comprises the steps of: partitioning the logic network into a first sub-network that operates only in response to a first clock signal; and partitioning the logic network into a second sub-network that operates only in response to a second clock signal.
Claim 9
Independent Claim
115 words
A method simulating a logic network having multiple clocks, the method comprising the steps of: identifying one or more combinational logic elements in the logic network having input signals that do not derive from sequential logic elements controlled by a single clock signal; and re-timing each of the one or more combinational logic elements forward through one or more sequential logic elements, thereby creating a first set of one or more combinational logic elements having input signals that derive from sequential logic elements controlled by a first clock signal, and a second set of one or more combinational logic elements having input signals that derive from sequential logic elements controlled by a second clock signal.
Claim 10
Independent Claim
115 words
A method simulating a logic network having multiple clocks, the method comprising the steps of: identifying one or more combinational logic elements in the logic network having input signals that do not derive from sequential logic elements controlled by a single clock signal; and re-timing each of the one or more combinational logic elements forward through one or more sequential logic elements, thereby creating a first set of one or more combinational logic elements having input signals that derive from sequential logic elements controlled by a first clock signal, and a second set of one or more combinational logic elements having input signals that derive from sequential logic elements controlled by a second clock signal.
Claim 11
Dependent Claim
48 words
The method of claim 8 , further comprising the step of partitioning the logic network into a plurality of sub-networks, including a first sub-network that operates only in response to the first clock signal, and a second sub-network that operates only in response to the second clock signal.
Claim 12
Independent Claim
117 words
A method of simulating a logic network having multiple clocks, the method comprising the steps of: identifying a set of one or more combinational logic elements in the logic network, wherein at least one of the one or more combinational logic elements is coupled to receive a first input signal triggered by a first clock signal and a second input signal triggered by a second clock signal; and re-timing each of the one or more combinational logic elements forward through one or more sequential logic elements, thereby providing re-timed combinational logic elements, each being coupled to receive input signals that that are triggered by either the first clock signal or the second clock signal, but not both.
Claim 13
Independent Claim
117 words
A method of simulating a logic network having multiple clocks, the method comprising the steps of: identifying a set of one or more combinational logic elements in the logic network, wherein at least one of the one or more combinational logic elements is coupled to receive a first input signal triggered by a first clock signal and a second input signal triggered by a second clock signal; and re-timing each of the one or more combinational logic elements forward through one or more sequential logic elements, thereby providing re-timed combinational logic elements, each being coupled to receive input signals that that are triggered by either the first clock signal or the second clock signal, but not both.
Claim 14
Dependent Claim
72 words
The method of claim 10 , further comprising the steps of: partitioning the logic network into a first sub-network that includes the re-timed combinational logic elements that are coupled to receive input signals that are triggered by the first clock signal; and partitioning the logic network into a second sub-network that includes the re-timed combinational logic elements that are coupled to receive input signals that are triggered by the second clock signal.
Claim 15
Independent Claim
143 words
A method of simulating a logic network having multiple clocks, the method comprising the steps of: identifying within the logic network a first sequential logic element controlled by a first clock signal, a second sequential logic element controlled by a second clock signal, and a combinational logic element providing a logic signal to the first and second sequential logic elements in response to a plurality of input signals; duplicating the combinational logic element, thereby providing a first combinational logic element and a second combinational logic element; routing the plurality of input signals to the first combinational logic element through a corresponding plurality of sequential logic elements, each being controlled by the first clock signal; and routing the plurality of input signals to the second combinational logic element through a corresponding plurality of sequential logic elements, each being controlled by the second clock signal.
Claim 16
Independent Claim
143 words
A method of simulating a logic network having multiple clocks, the method comprising the steps of: identifying within the logic network a first sequential logic element controlled by a first clock signal, a second sequential logic element controlled by a second clock signal, and a combinational logic element providing a logic signal to the first and second sequential logic elements in response to a plurality of input signals; duplicating the combinational logic element, thereby providing a first combinational logic element and a second combinational logic element; routing the plurality of input signals to the first combinational logic element through a corresponding plurality of sequential logic elements, each being controlled by the first clock signal; and routing the plurality of input signals to the second combinational logic element through a corresponding plurality of sequential logic elements, each being controlled by the second clock signal.
Claim 17
Independent Claim
116 words
A method of simulating a logic network having multiple clocks, the method comprising the steps of: identifying within the logic network a sequential logic element controlled by a clock signal, and a combinational logic element providing a logic signal to the sequential logic element in response to N input signals, N being an integer greater than or equal to two; duplicating the sequential logic element, thereby providing N sequential logic elements controlled by the clock signal; applying each of the N input signals to a corresponding one of the N sequential logic elements; and routing the N input signals to the combinational logic element through the N sequential logic elements in response to the clock signal.
Claim 18
Independent Claim
116 words
A method of simulating a logic network having multiple clocks, the method comprising the steps of: identifying within the logic network a sequential logic element controlled by a clock signal, and a combinational logic element providing a logic signal to the sequential logic element in response to N input signals, N being an integer greater than or equal to two; duplicating the sequential logic element, thereby providing N sequential logic elements controlled by the clock signal; applying each of the N input signals to a corresponding one of the N sequential logic elements; and routing the N input signals to the combinational logic element through the N sequential logic elements in response to the clock signal.
References Cited (Backward Citations)
US3775756A
Cited
US4237545A
Cited
JPS53121537A
Cited
US4189782A
Cited
US4288658A
Cited
US4434461A
Cited
US4594661A
Cited
US4661901A
Cited
US4750155A
Cited
US4821233A
Cited
US5042004A
Cited
US5019996A
Cited
US5426744A
Cited
US5081375A
Cited
US5053995A
Cited
EP0410759A2
Cited
US5185706A
Cited
US5469368A
Cited
US5553002A
Cited
US5144242A
Cited
US5245227A
Cited
US5155390A
Cited
US5469577A
Cited
US5513124A
Cited
US5224056A
Cited
US5426738A
Cited
US5377331A
Cited
US5521835A
Cited
US5432388A
Cited
US5349248A
Cited
WO1994028475A1
Cited
US5530654A
Cited
WO1995022205A1
Cited
US5426378A
Cited
US5526276A
Cited
US6009531A
Cited
US5583450A
Cited
US5600263A
Cited
US5629637A
Cited
US5646545A
Cited
US5701441A
Cited
US5978260A
Cited
US6263430B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-11-11 | 2006-05-13 | 2006-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-11-11 | 2010-05-13 | 2010-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-11-11 | 2014-05-13 | 2014-11-12 | $7700.00 | Window Closed / Lapsed |