Programmable power supply level detection and initialization circuitry

Claim 3

The apparatus of claim 1, wherein the programmable logic means is further connected to receive at least one general purpose input signal in response to which the programmable logic means generates the control signals.

Claim 4

The apparatus of claim 1, wherein the programmable logic means comprises: a programmable AND-plane including a plurality of programmable AND-gates, each AND-gate accepting a programmable combination of AND-input signals and generating therefrom a product term; and a fixed-OR array including a plurality of OR-gates, each OR-gate being hardwired to accept the product terms from a plurality of the AND-gates and generating therefrom a sum-of-products term; wherein the AND-input signals include the threshold signal; and the sum-of-products terms include the control signals.

Claim 5

The apparatus of claim 1, further including: hardwired programmable means for supplying the reference signal.

Claim 6

The apparatus of claim 2, wherein the programmable logic means comprises: programmable logic having a plurality of array inputs connected to receive the threshold signal and the at least one general purpose input signal, the programmable logic supplying a plurality of array outputs in response to a programmable combination of signals supplied to the plurality of array inputs; and a plurality of output circuits, each connected to receive at least one array output of the plurality of array outputs and supplying one control signal of the control signals in response to the at least one array output.

Claim 7

The apparatus of claim 5 wherein each given output circuit of the plurality of output circuits includes means for programming a power-up state for the respective one control signal received by the given output circuit.

Claim 8

The apparatus of claim 5 further including: a counter having a counter control input and a set of counter outputs, wherein the counter control input is connected to one array output of the plurality of array outputs and the set of counter outputs is connected to the plurality of array inputs.

Claim 9

The apparatus of claim 5 further including: a plurality of state register means, each connected to receive at least one array output of the plurality of array outputs, each state register means for supplying a respective state output of a plurality of state outputs and wherein the plurality of state outputs of the plurality of state register means are connected to the plurality of array inputs.

Claim 10

The apparatus of claim 5 further including: means, connected to the power supply, for generating an undervoltage signal for supply to the programmable logic while the output level is below a prespecified threshold.

Claim 11

The apparatus of claim 9 further including: register means, connected to receive the undervoltage signal, for generating a reset signal and for providing the reset signal to the plurality of array inputs.

Claim 14

The apparatus of claim 11, wherein the programmable logic array comprises: a programmable AND-plane including a plurality of programmable AND-gates, each AND-gate accepting a programmable combination of the one or more signals which the array inputs are connected to receive and generating therefrom a product term; and a fixed-OR array including a plurality of OR-gates, each OR-gate being hardwired to accept the product terms from a plurality of the AND-gates and generating therefrom a respective one of the array outputs in the form of a sum-of-products term.

Claim 15

The apparatus of claim 11, wherein the array inputs are further connected to receive at least one general purpose input signal in response to which the programmable logic means generates the control signals.

Claim 16

The apparatus of claim 13, wherein the programmable logic means further comprises: a plurality of output circuits, each connected to receive at least one array output of the plurality of array outputs and supplying a given control signal of the plurality of control signals in response to the at least one array output.

Claim 17

The apparatus of claim 14, wherein each given output circuit of the plurality of output circuits includes means for programming a power-up state for the given control signal supplied by the given output circuit.

Claim 18

The apparatus of claim 14, further including: a counter having a counter control input and a set of counter outputs, wherein the counter control input is connected to one array output of the plurality of array outputs, and the set of counter outputs is connected to the plurality of array inputs.

Claim 19

The apparatus of claim 14, further including: a plurality of state register means, each connected to receive at least one array output of the plurality of array outputs, each state register means for supplying a respective state output of a plurality of state outputs, and wherein the plurality of state outputs of the plurality of state register means are connected to the plurality of array inputs.

Claim 20

The apparatus of claim 14, further including: means, connected to the power supply, for generating an undervoltage signal for supply to the programmable logic means while the output level is below a prespecified level.

Claim 21

The apparatus of claim 18, further including: register means, connected to receive the undervoltage signal, for generating a reset signal and for providing the reset signal to the plurality of array inputs.

Claim 24

The apparatus of claim 20, wherein the programmable logic means comprises; a programmable AND-plane including a plurality of programmable AND-gates, each AND-gate accepting a programmable combination of AND-input signals and generating therefrom a product term; and a fixed-OR array including a plurality of OR-gates, each OR-gate being hardwired to accept the product terms from a plurality of the AND-gates and generating therefrom a sum-of-products term; wherein the AND-input signals include the plurality of general purpose signals and the plurality of voltage threshold signals; and the sum-of-products terms include the control signals.

Claim 25

The apparatus of claim 20, wherein the programmable logic means comprises: programmable logic having a plurality of array inputs connected to receive the plurality of voltage threshold signals and the plurality of general purpose signals, the programmable logic supplying a plurality of array outputs in response to a programmable combination of signals supplied to the plurality of array inputs; and a plurality of output circuits, each connected to receive at least one array output of the plurality of array outputs and supplying a given control signal of the plurality of control signals in response to the at least one array output.

Claim 26

The apparatus of claim 22, wherein each given output circuit of the plurality of output circuits includes means for programming a power-up state for the given control signal supplied by the given output circuit.

Claim 27

The apparatus of claim 22, further including: a counter having a counter control input and a set of counter outputs, wherein the counter control input is connected to one array output of the plurality of array outputs, and the set of counter outputs is connected to the plurality of array inputs.

Claim 28

The apparatus of claim 22, further including: a plurality of state register means, each connected to receive at least one array output of the plurality of array outputs, each state register means for supplying a given state output of a plurality of state outputs, and wherein the plurality of state outputs of the plurality of state register means are connected to the plurality of array inputs.

Claim 29

The apparatus of claim 22, further including: register means, connected to receive the undervoltage signal, for generating a reset signal and for providing the reset signal to the plurality of array inputs.

Claim 30

An integrated circuit for generating control signals for supply to and control of a signal processing system, the integrated circuit and the signal processing system each being connected to a power supply having an output level and to a clock, the integrated circuit comprising: means, connected to the power supply, for generating an undervoltage signal while the output level is below a prespecified threshold; means for supplying a plurality of programmable signals, each programmable signal indicating a programmable threshold; means, connected to the power supply and to receive the plurality of programmable signals, for generating a plurality of voltage threshold signals, each given voltage threshold signal corresponding to a given programmable signal and having a first state while the output level is below a given programmable threshold indicated by the given corresponding programmable signal and having a second state while the output level is above the given programmable threshold; means for supplying a plurality of general purpose signals; programmable logic having a plurality of array inputs connected to receive the undervoltage signal, the plurality of voltage threshold signals, the plurality of general purpose signals and the clock signal, the programmable logic supplying a plurality of array outputs in response to a programmable combination of signals supplied to the plurality of array inputs; and a plurality of output circuits, each connected to receive at least one array output of the plurality of array outputs and supplying a given control signal of the control signals in response to the at least one array output.

Claim 31

An integrated circuit for generating control signals for supply to and control of a signal processing system, the integrated circuit and the signal processing system each being connected to a power supply having an output level and to a clock, the integrated circuit comprising: means, connected to the power supply, for generating an undervoltage signal while the output level is below a prespecified threshold; means for supplying a plurality of programmable signals, each programmable signal indicating a programmable threshold; means, connected to the power supply and to receive the plurality of programmable signals, for generating a plurality of voltage threshold signals, each given voltage threshold signal corresponding to a given programmable signal and having a first state while the output level is below a given programmable threshold indicated by the given corresponding programmable signal and having a second state while the output level is above the given programmable threshold; means for supplying a plurality of general purpose signals; programmable logic having a plurality of array inputs connected to receive the undervoltage signal, the plurality of voltage threshold signals, the plurality of general purpose signals and the clock signal, the programmable logic supplying a plurality of array outputs in response to a programmable combination of signals supplied to the plurality of array inputs; and a plurality of output circuits, each connected to receive at least one array output of the plurality of array outputs and supplying a given control signal of the control signals in response to the at least one array output.

Claim 32

The integrated circuit of claim 27, wherein each given output circuit of the plurality of output circuits includes means for programming a power-up state for the given control signal supplied by the given output circuit.

Claim 33

The integrated circuit of claim 27, further including: a counter connected to receive the clock signal and having a counter control input and a set of counter outputs, wherein the counter control input is connected to one array output of the plurality of array outputs, and the set of counter outputs is connected to the plurality of array inputs.

Claim 34

The integrated circuit of claim 27, further including: a plurality of state register means, each connected to receive at least one array output of the plurality of array outputs, each state register means for supplying a respective state output of a plurality of state outputs, and wherein the plurality of state outputs of the plurality of state register means are connected to the plurality of array inputs.

Claim 35

The integrated circuit of claim 27, further including: register means, connected to receive the undervoltage signal and the clock signal, for generating a reset signal synchronized with the clock signal, and for providing the reset signal to the plurality of array inputs.

Claim 38

The apparatus of claim 32 wherein: the apparatus further comprises counter means for generating a counter output signal in response to one of the logic array output signals; and the programmable combination further includes the counter output signal.

Claim 39

The apparatus of claim 32 wherein: the apparatus further comprises one or more state register means, each for generating at least one state output signal in response to one or more of the logic array output signals; and the programmable combination further includes the at least one state output signal.

Claim 40

The apparatus of claim 32 wherein: the apparatus further comprises means, connected to the power supply, for generating a reset signal when the output level is below a prespecified threshold; and the programmable combination further includes the reset signal.

Claim 41

The apparatus of claim 32, wherein the programmable logic means comprises: a programmable AND-plane including a plurality of AND-gates each having inputs programmably couplable to respective ones of the logic array inputs, and each having an output; and a fixed OR-plane including a plurality of OR-gates each having inputs hardwired to the outputs of a plurality of the AND-gates, and each having an output coupled to a respective one of the logic array outputs.

Claim 42

The apparatus of claim 32, wherein: the plurality of logic array inputs are further connected to receive at least one general purpose input signal; and the programmable combination further includes the at least one general purpose input signal.

Claim 43

The apparatus of claim 37 wherein each given output means comprises: means for programming a power-up state for the respective supplied by the plurality of power-up initialization control signals supplied by the given output means.