LSI logic synthesis device and method therefor

Claim 2

A logic synthesis device for LSI comprising: a logic description information file for storing, for said LSI having a configuration with a plurality of hierarchical blocks given through hierarchical design, logic description information in a certain design description language describing logic operation contents of said LSI for each of said hierarchical blocks; a block placement information file for storing information about location and area on LSI of the hierarchical blocks constituting said LSI; a library file for storing the correspondence information between the logic operation contents described in said logic description information and the logic gate circuits physically realized on said LSI; and logic synthesis means for making logic synthesis in each of said hierarchical blocks and between said hierarchical blocks based on said logic description information and said correspondence information and adjusting the delay time between said hierarchical blocks based on said block placement information.

Claim 3

A logic synthesis device for LSI as set forth in claim 1, wherein said logic synthesis means further comprises means for performing said logic synthesis using said block placement information and said correspondence information for each of said hierarchical blocks; and delay adjustment means for adjusting the delay time between said hierarchical blocks by considering the distance between said hierarchical blocks obtained from said block placement information so that the delay time between said hierarchical blocks satisfies a predetermined delay time as a condition.

Claim 4

A logic synthesis device for LSI as set forth in claim 2, wherein said logic synthesis means further comprises judgment means for judging whether the delay time between said blocks as a result of said delay time adjustment satisfies the predetermined delay time.

Claim 5

A logic synthesis device for LSI as set forth in claim 2, wherein said delay adjustment means of said logic synthesis means changes, deletes or adds logic gate circuit(s) of said hierarchical block where said logic synthesis is executed so that the delay time between said hierarchical blocks satisfy the predetermined delay time.

Claim 6

A logic synthesis circuit for LSI as set forth in claim 1, wherein said logic synthesis means further comprises means for performing said logic synthesis using said block placement information and said correspondence information for each of said hierarchical blocks; and judgment means for judging whether said each of said hierarchical blocks where said logic synthesis is made can be settled within the area specified in said block placement information.

Claim 7

A logic synthesis circuit for LSI as set forth in claim 1, wherein said block placement information file stores, as the information about location and area on LSI of the hierarchical blocks constituting the LSI, values on two-dimensional coordinates with two reference axes intersection at right angles to indicate a location on LSI of vertexes of a quadrilateral, which is a shape of an individual hierarchical block.

Claim 8

A logic synthesis device for LSI comprising: a logic description information file for storing, for said LSI having a configuration with a plurality of hierarchical blocks given through hierarchical design, logic description information in a certain design description language describing logic operation contents of said LSI for each of said hierarchical blocks; a block placement information file which stores information about location and area on LSI of the hierarchical blocks constituting said LSI; a library which stores correspondence information between the logic operation contents described in said logic description information and the logic gate circuits physically realized on said LSI; and logic synthesis means for performing logic synthesis in each of said hierarchical blocks and between said hierarchical blocks based on said logic description information and said correspondence information and adjusting the delay time between said hierarchical blocks based on said block placement information; wherein said logic synthesis means further comprising means for performing said logic synthesis based on said block placement information and said correspondence information for each of said hierarchical blocks; judgment means for judging whether said each of said hierarchical blocks where said logic synthesis is made can be settled within the area specified in said block placement information; and delay adjustment means for adjusting the delay time between said hierarchical blocks with considering a distance between said hierarchical blocks obtained from said block placement information.

Claim 9

A logic synthesis device for LSI comprising: a logic description information file for storing, for said LSI having a configuration with a plurality of hierarchical blocks given through hierarchical design, logic description information in a certain design description language describing logic operation contents of said LSI for each of said hierarchical blocks; a block placement information file which stores information about location and area on LSI of the hierarchical blocks constituting said LSI; a library which stores correspondence information between the logic operation contents described in said logic description information and the logic gate circuits physically realized on said LSI; and logic synthesis means for performing logic synthesis in each of said hierarchical blocks and between said hierarchical blocks based on said logic description information and said correspondence information and adjusting the delay time between said hierarchical blocks based on said block placement information; wherein said logic synthesis means further comprising means for performing said logic synthesis based on said block placement information and said correspondence information for each of said hierarchical blocks; judgment means for judging whether said each of said hierarchical blocks where said logic synthesis is made can be settled within the area specified in said block placement information; and delay adjustment means for adjusting the delay time between said hierarchical blocks with considering a distance between said hierarchical blocks obtained from said block placement information.

Claim 10

A logic synthesis device for LSI as set forth in claim 7, wherein said delay adjustment means of said logic synthesis means changes, deletes or adds logic gate circuit(s) of said each of said hierarchical block where said logic synthesis is executed so that the delay time between said hierarchical blocks satisfies the predetermined delay time.

Claim 11

A logic synthesis device for LSI as set forth in claim 8, wherein said logic synthesis means further comprises judgment means to judge whether the delay time between said hierarchical blocks as a result of said delay time adjustment satisfies the predetermined delay time as condition.

Claim 12

A logic synthesis device for LSI as set forth in claim 7, wherein said LSI block placement information file stores, as the information about location and area on LSI of the hierarchical blocks constituting the LSI, values on two-dimensional coordinates with two reference axes intersecting at right angles to show a location on LSI of vertexes of a quadrilateral, which is a shape of an individual hierarchical block.

Claim 13

A logic synthesis method for LSI having a configuration divided into a plurality of hierarchical blocks specified by hierarchical design, logic description information in a certain design description language describing the logic operation contents of said LSI for each of said hierarchical blocks, a block placement information about location and area on LSI of the hierarchical blocks constituting said LSI and correspondence information between logic operation contents described in said logic description information and the logic gate circuits physically realized on said LSI, comprising the steps of: a logic synthesis step of performing logic synthesis in each of said hierarchical blocks and between said hierarchical blocks for each of said hierarchical blocks based on said logic description information and said correspondence information; and an adjustment step of making adjustment so that a delay time between said hierarchical blocks satisfies the delay time predetermined as conditions with considering the distance between said hierarchical blocks obtained from said block placement information.

Claim 14

A logic synthesis method for LSI having a configuration divided into a plurality of hierarchical blocks specified by hierarchical design, logic description information in a certain design description language describing the logic operation contents of said LSI for each of said hierarchical blocks, a block placement information about location and area on LSI of the hierarchical blocks constituting said LSI and correspondence information between logic operation contents described in said logic description information and the logic gate circuits physically realized on said LSI, comprising the steps of: a logic synthesis step of performing logic synthesis in each of said hierarchical blocks and between said hierarchical blocks for each of said hierarchical blocks based on said logic description information and said correspondence information; and an adjustment step of making adjustment so that a delay time between said hierarchical blocks satisfies the delay time predetermined as conditions with considering the distance between said hierarchical blocks obtained from said block placement information.

Claim 15

A logic synthesis method for LSI as set forth in claim 11, wherein further comprising the step of: judging whether said each of said hierarchical blocks where said logic synthesis is executed can be settled within the area specified in said block placement information.

Claim 16

A logic synthesis method for LSI as set forth in claim 11, wherein said delay time adjustment step changes, deletes or adds logic gate circuit(s) for said each of said hierarchical blocks where said logic synthesis is executed so that the delay time between said hierarchical blocks satisfies the predetermined delay time as a condition.

Claim 17

A logic synthesis method for LSI as set forth in claim 11, further comprising a step to judge whether the delay time between said hierarchical blocks as a result of said delay time adjustment satisfies said predetermined delay time as a condition.