Logical synthesis

Claim 3

The method recited in claim 1 wherein said logical reduction on said expressions is performed by: removing inverters from said expression, performing all reduction of simple blocks feeding simple blocks which compress to simple blocks, performing all reduction of simple blocks feeding simple blocks which compress to grouped blocks, performing all reduction of grouped blocks feeding simple blocks which compress to grouped blocks, performing all reduction of simple blocks feeding grouped blocks which compress to grouped blocks.

Claim 4

The method recited in claim 1 wherein said process is performed recursively.

Claim 5

A method as set forth in claim 1 further comprising the computerized step of modeling a logic circuit based on the logical function blocks after the step of logical reduction on said primitive blocks.

Claim 6

A method as set forth in claim 1 wherein said individual expressions are in prefix form.

Claim 9

The method recited in claim 6 wherein said inverters are removed by: a computerized method of inverter circuit reduction, each circuit being described by an expression including operands and operators in prefix notation, the operators including inverters, said method including the steps of: recursively operating on any inner expression such that the operands are processed left to right during said recursive operation, one of the expression's operators being an inverter and its operand being an operator, and if the inner expression's operator is an inverter replacing the expression by the operand of the inner expression, otherwise, inverting the expression's operator and replacing its operand with the inner expression's operand, if another one of the expression's operator is not an inverter and all of tis operands are inverter inner expressions, then performing a De Morgan translation on the expression and replacing its operands by the operands of the inverter inner expressions, whereby the resulting expression will represent a circuit which has been reduced if possible.

Claim 10

A method as set forth in claim 6 further comprising the subsequent computerized step of modeling a logic circuit based in part on the simple and grouped blocks resulting after said reduction steps.

Claim 11

A method as set forth in claim 6 wherein all of said steps are performed on an expression, said expression comprising a character string of a plurality of operators and a plurality of associated operands.

Claim 12

A method as set forth in claim 9 further comprising the step of removing inverters from said expression before performing reduction of simple blocks feeding simple blocks.

Claim 15

The method recited in claim 11 wherein said process is performed recursively.

Claim 16

A method as set forth in claim 11 further comprising the subsequent computerized step of modeling a logic circuit based in part on the inverter reduced expression.

Claim 17

A logic level reduction process to perform all the required reductions within a group of logic, said process being independent of the partitioning of the possibilities, and complete reduction occurring after procession for all groups, said process beginning with an expression including a plurality of operators and a plurality of associated operands in prefix form, being implemented by a computer, and comprising the steps of: recursively operating on any expression, each of said expressions including a plurality of operands which are processed left to right during said recursive operation, at least one operand being an inner expression with a compressible operator, and no operand being incompatible with this compression, and further comprising the steps of: changing the expression operator to the compressed operator and replacing compressible inner expressions with their operands, and wherein said expression is initially reduced such that simple logic elements feeding simple logic elements are reduced to simple logic elements, and subsequently reduced such that simple logic elements feeding simple logic elements are reduced to grouped logic elements.

Claim 18

A logic level reduction process to perform all the required reductions within a group of logic, said process being independent of the partitioning of the possibilities, and complete reduction occurring after procession for all groups, said process beginning with an expression including a plurality of operators and a plurality of associated operands in prefix form, being implemented by a computer, and comprising the steps of: recursively operating on any expression, each of said expressions including a plurality of operands which are processed left to right during said recursive operation, at least one operand being an inner expression with a compressible operator, and no operand being incompatible with this compression, and further comprising the steps of: changing the expression operator to the compressed operator and replacing compressible inner expressions with their operands, and wherein said expression is initially reduced such that simple logic elements feeding simple logic elements are reduced to simple logic elements, and subsequently reduced such that simple logic elements feeding simple logic elements are reduced to grouped logic elements.

Claim 19

The method recited in claim 14 wherein said process is performed recursively.

Claim 20

A method as set forth in claim 14 further comprising the subsequent computerized step of modeling a logic circuit based in part on the reduced expression.

Claim 21

The process of creating logic block representation from an expression representing said logic, said logic block representation of the expression including definitions of the input pins, the output pins and logic block interconnections, said process being implemented by a computer and including the following steps: recursively operating on any inner expressions, each of said expressions including a plurality of operands which are processed left to right during said recursive operation, and for a first operand in the expression, creating a logic block whose function is the same as the expression's operator and adding an output pin to the block, adding an input pin to the block and connecting to the operand's source for all operands, and returning the output pin of each operator block as a source to the adjacent block corresponding to the leftward-operator, if any, when all operands have been processed.

Claim 22

The process of creating logic block representation from an expression representing said logic, said logic block representation of the expression including definitions of the input pins, the output pins and logic block interconnections, said process being implemented by a computer and including the following steps: recursively operating on any inner expressions, each of said expressions including a plurality of operands which are processed left to right during said recursive operation, and for a first operand in the expression, creating a logic block whose function is the same as the expression's operator and adding an output pin to the block, adding an input pin to the block and connecting to the operand's source for all operands, and returning the output pin of each operator block as a source to the adjacent block corresponding to the leftward-operator, if any, when all operands have been processed.

Claim 23

The method recited in claim 17 wherein said process is performed recursively.

Claim 26

The method recited in claim 13 wherein the logical reduction of said expressions produces non primitive blocks.

Claim 27

A method as set forth in claim 19 further comprising the subsequent computerized step of modeling a logic circuit corresponding to the globally reduced logical function blocks.

Claim 28

A method as set forth in claim 19 wherein each of individual expressions is in prefix form.

Claim 29

A single pass method of performing logical reduction on a set of logical blocks represented by an expression, said method comprising the following steps in order: removing inverters from said expression, performing all reduction of simple blocks feeding simple blocks which compress to simple blocks, performing all reduction of simple blocks feeding simple blocks which compress to grouped blocks, performing all reduction of grouped blocks feeding simple blocks which compress to grouped blocks, performing all reduction of simple blocks feeding grouped blocks which compress to grouped blocks, whereby all reductions are completed in one pass, and wherein all of said reduction steps are performed by a computer.

Claim 30

A single pass method of performing logical reduction on a set of logical blocks represented by an expression, said method comprising the following steps in order: removing inverters from said expression, performing all reduction of simple blocks feeding simple blocks which compress to simple blocks, performing all reduction of simple blocks feeding simple blocks which compress to grouped blocks, performing all reduction of grouped blocks feeding simple blocks which compress to grouped blocks, performing all reduction of simple blocks feeding grouped blocks which compress to grouped blocks, whereby all reductions are completed in one pass, and wherein all of said reduction steps are performed by a computer.

Claim 31

The method recited in claim 23 where said expressions are in prefix form.