EP0168650A2
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EP
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Method of designing a logic circuitry
Assignee: International Business Machines Corp
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Filing: 1985-06-19
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Granted: —
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Expires: 2005-06-19
Abstract
Abstract Logic is synthesized from a flowchart-level description by first generating an AND/OR logic design (104), simplifying the AND/OR logic, converting the AND/OR logic to NAND or NOR logic (106), applying particular sequences of simplifying transformations to the NAND or NOR logic, converting the simplified NAND or NOR logic to a target technology (108), and simplifying the target technology where possible. The end result is an interconnection of primitives of the target technology in a language from which automated logic diagrams can be produced.
Inventors
- 👤 John A. Darringer
- 👤 William Henry Joyner, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 15:27
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
152 words
A method of designing a logic circuitry implementation in a desired technology from a description of operating characteristics to be provided by said logic circuitry, characterized by the steps of: generating a first logic circuit design (104) in accordance with the description; simplifying said first logic design; converting the simplified first logic design to a second logic design (106) in a logic system requiring fewer different logic operators than in said first logic design and comprising a plurality of interconnected cells and performing equivalent functions; simplifying said second logic design, the step of simplifying the second logic design comprising the steps of: applying a first sequence of logic transformations for reducing the depth of the second logic design; and applying a second sequence of logic transformations for reducing the size while possibly increasing the depth of the second logic design; and converting said simplified second logic design to said desired technology (108).
Claim 2
Independent Claim
152 words
A method of designing a logic circuitry implementation in a desired technology from a description of operating characteristics to be provided by said logic circuitry, characterized by the steps of: generating a first logic circuit design (104) in accordance with the description; simplifying said first logic design; converting the simplified first logic design to a second logic design (106) in a logic system requiring fewer different logic operators than in said first logic design and comprising a plurality of interconnected cells and performing equivalent functions; simplifying said second logic design, the step of simplifying the second logic design comprising the steps of: applying a first sequence of logic transformations for reducing the depth of the second logic design; and applying a second sequence of logic transformations for reducing the size while possibly increasing the depth of the second logic design; and converting said simplified second logic design to said desired technology (108).
Claim 3
Dependent Claim
49 words
A method as defined in Claim 1, wherein the step of applying said first sequence of logic transformations comprises: applying a first logic transformation set for reducing logic depth; applying a second logic transformation set for reducing redundancy; and applying a third logic transformation set for eliminating common terms.
Claim 4
Dependent Claim
56 words
A method as defined in Claim 1 and 2, wherein the step of applying said second sequence of logic transformations comprises: applying a fourth logic transformation set for reducing logic size while possibly increasing logic depth; applying a fifth logic transformation set for reducing redundancy; and applying a sixth logic transformation set for eliminating common terms.
Claim 5
Dependent Claim
72 words
A method as defined in Claim 2 and 3, wherein said second and fifth logic transformation sets include at least one common logic transformation, said common logic transformation being applied in the first sequence regardless whether said common logic transformation will increase the number of cells in the second logic design and being applied in the second sequence only if it will not result in an increase in the number of cells.
Claim 6
Dependent Claim
46 words
A method as defined in Claim 1, wherein the step of applying said second sequence of logic transformations comprises applying a first logic transformation (e.g., FACTORN) for reducing a fan-in characteristic of some portions of the second logic design in accordance with a first fan-in value.
Claim 7
Dependent Claim
41 words
A method as defined in Claim 1, further comprising the step of applying a third sequence of logic transformations for reducing the number of cells in the second logic design, said third sequence being applied between the first and second sequences.
Claim 8
Dependent Claim
42 words
A method as defined in Claim 6, wherein said third sequence of logic transformations includes a first set of logic transformations followed by a second set of logic transformations, said second set of logic transformations comprising said first sequence of logic transformations.
Claim 9
Dependent Claim
66 words
A method as defined in Claim 1 and 6, wherein said desired technology has a maximum allowable fan-in valve, the step of applying said second sequence of logic transformations comprising applying a first logic transformation (e. g ., FACTORN) for reducing a fan-in characteristic of some portions of the second logic design in accordance with a desired fan-in vlaue less than said maximum allowable fan-in value.
Claim 10
Dependent Claim
39 words
A method as defined in Claim 8, further comprising the step of correcting the fan-in characteristics of the second logic design in accordance with said maximum allowable fan-in value subsequent to application of said second sequence of logic transformations.
Claim 11
Dependent Claim
46 words
A method as defined in Claim 1 and 7, wherein said step of applying said first sequence of logic transformations further comprises applying a fourth logic transformation set (NTR8) for further reducing the logic depth while increasing the number of cells in the second logic design.
Claim 12
Dependent Claim
122 words
A method as defined in Claim 1, wherein said converting step for converting said simplified second logic design to said desired technology further comprising the step of simplifying the hardware design, said hardware simplifying step comprising: applying a first hardware transformation set for substituting technology-specific books for predetermined patterns of said hardware primitive; dotting signal lines to decrease the number of components in said hardware logic design, and to decrease fan-in some portions of said hardware logic design even if the number of components in said portions is not decreased; applying said first hardware transformation set; correcting fan-out in said hardware logic design to a desired value; adjusting path lengths in said hardware logic design; and correcting fan-out to said desired value.
Claim 13
Dependent Claim
29 words
A method as defined in Claim 1, wherein said first sequence of logic transformations is applied a plurality of times prior to applying said second sequence of logic transformations.
Claim 14
Dependent Claim
27 words
A method as defined in Claim 1, wherein said first logic design is implemented in AND/OR logic and said second logic design is implemented in NAND logic.
Claim 15
Dependent Claim
27 words
A method as defined in Claim 1, wherein said first logic design is implemented in AND/OR logic and said second logic design is implemented in NOR logic.
Claim 16
Dependent Claim
32 words
A method as defined in Claim 11, wherein said step of simplifying said hardware design further comprises applying said first hardware transformation set after the dotting step but before the adjusting step.
Claim 17
Dependent Claim
44 words
A method as defined in Claim 11, wherein said step of simplifying said hardware logic design further comprises the step of correcting said fan-out in the hardware logic design after said second application of the first hardware transformation set and before the adjusting step.
Claim 18
Dependent Claim
92 words
A method as defined in Claim 11, wherein said hardware logic design includes inverters receiving and inverting outputs from associated components, and wherein, when the desired technology is a dual-rail technology, the step of simplifying the hardware design further comprises the step of applying a dual-rail transformation for removing some of the inverters by substituting for said inverter and opposite-phase output signal available from its associated component, said dual-rail conversion transformation being applied both prior to the step of applying the first hardware transformation and subsequent to the step of correcting fan-out.
Claim 19
Independent Claim
165 words
A method of designing a logic circuitry implementation in a desired technology from a description of operating characteristics to be provided by said logic circuitry, characterized by the steps of: generating a first logic circuit design (104) in accordance with the description; simplifying said first logic design; converting the simplified first logic design to a second logic design (106) in a logic system requiring fewer different logic operators than in said first logic design; simplifying said second logic design; converting the simplified second logic design to a hardware design (108) in said desired technology comprising a plurality of interconnected hardware components; and simplifying said hardware logic design, the step of simplifying hardware logic design comprising selectively applying first or second hardware transformation sets for substituting technology-specific components for predetermined patterns of the hardware components, said first hardware transformation set resulting in fewer components than the second hardware transformation set and said second hardware transformation set resulting in higher-speed logic than the first hardware transformation set.
Claim 20
Independent Claim
165 words
A method of designing a logic circuitry implementation in a desired technology from a description of operating characteristics to be provided by said logic circuitry, characterized by the steps of: generating a first logic circuit design (104) in accordance with the description; simplifying said first logic design; converting the simplified first logic design to a second logic design (106) in a logic system requiring fewer different logic operators than in said first logic design; simplifying said second logic design; converting the simplified second logic design to a hardware design (108) in said desired technology comprising a plurality of interconnected hardware components; and simplifying said hardware logic design, the step of simplifying hardware logic design comprising selectively applying first or second hardware transformation sets for substituting technology-specific components for predetermined patterns of the hardware components, said first hardware transformation set resulting in fewer components than the second hardware transformation set and said second hardware transformation set resulting in higher-speed logic than the first hardware transformation set.
References Cited (Backward Citations)
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