US5287289A
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Logic synthesis method
Assignee: Hitachi Ltd
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Filing: 1991-04-09
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Granted: 1994-02-15
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Expires: 2011-04-09
Abstract
Abstract A logic circuit the functions of which have been expressed by a Boolean expression is subdivided, and then each of the subdivided logic circuit portions corresponds to each of the Boolean expressions. A plurality of logic circuits whose functions are equal to each other, whose delay times and gate numbers are different from each other, are synthesized every subdivided circuit portions, and a restriction condition formula is formed by employing the synthesized logic circuit under a restriction condition of the delay time designated by a user. While a linear programming is applied under the restriction condition and the number of gates is used as an objective function, such a logic circuit that the objective function takes a stationary value (a minimum value in the present invention) is selected with respect to each of subdivided portions, whereby an overall logic circuit is constructed.
Inventors
- 👤 Naohiro Kageyama
- 👤 Chihei Miura
- 👤 Tsuguo Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 10:54
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
300 words
A method, executed by a computer, of modifying a digital logic circuit represented by a Boolean expression comprised of a plurality of portions each of which is represented by a Boolean expression, said method comprising the steps of: forming a plurality of groups of logic circuits each represented by a Boolean expression, where each group corresponds to one of said plurality of portions, wherein Boolean expressions which represent logic circuits of each group are equivalent in function to a Boolean expression which represents one of said corresponding portions and are formed by modifying said Boolean expression which represents the corresponding portion, so that one of the logic circuits of each group will have a delay time and a gate number which is different from others of said logic circuits of said each group, in a case where the logic circuits of each group are realized by logic gates of predetermined kinds; forming, as candidates for a digital logic circuit after modification, plural combinations each comprised of a plurality of logic circuits each represented by a Boolean expression, each logic circuit representing a Boolean expression corresponding to one of said portions and being selected from a group of logic circuits formed for said corresponding portion by said forming a plurality of groups step; evaluating a delay time and a total number of logic gates of each combination, in a case where the logic circuits represented by Boolean expressions which constitute said each combination are realized by logic gates of said predetermined kinds; and selecting one of the combinations which will have a delay time which is less than or equal to a predetermined delay time and a total number of logic gates which is minimized among said combinations, as a new digital logic circuit after modification of said digital logic circuit.
Claim 2
Independent Claim
300 words
A method, executed by a computer, of modifying a digital logic circuit represented by a Boolean expression comprised of a plurality of portions each of which is represented by a Boolean expression, said method comprising the steps of: forming a plurality of groups of logic circuits each represented by a Boolean expression, where each group corresponds to one of said plurality of portions, wherein Boolean expressions which represent logic circuits of each group are equivalent in function to a Boolean expression which represents one of said corresponding portions and are formed by modifying said Boolean expression which represents the corresponding portion, so that one of the logic circuits of each group will have a delay time and a gate number which is different from others of said logic circuits of said each group, in a case where the logic circuits of each group are realized by logic gates of predetermined kinds; forming, as candidates for a digital logic circuit after modification, plural combinations each comprised of a plurality of logic circuits each represented by a Boolean expression, each logic circuit representing a Boolean expression corresponding to one of said portions and being selected from a group of logic circuits formed for said corresponding portion by said forming a plurality of groups step; evaluating a delay time and a total number of logic gates of each combination, in a case where the logic circuits represented by Boolean expressions which constitute said each combination are realized by logic gates of said predetermined kinds; and selecting one of the combinations which will have a delay time which is less than or equal to a predetermined delay time and a total number of logic gates which is minimized among said combinations, as a new digital logic circuit after modification of said digital logic circuit.
Claim 3
Dependent Claim
60 words
The method according to claim 1 wherein, a Boolean expression representing each of said plurality of portions comprises a sum of Boolean products; and, the forming step of said groups includes a step of modifying said Boolean expression representing each portion by factorizing said Boolean expression with respect to different ones of plural signals which appear in said Boolean expression.
Claim 4
Dependent Claim
77 words
The method according to claim 2 wherein, the forming step of said groups further includes a step of detecting whether plural ones of plural signals which appear in said Boolean expression representing said corresponding portion appear together in plural ones of product terms within said Boolean expression; and, said factorizing is executed with respect to a product of plural signals which have been detected as ones which appear together in plural products terms within said Boolean expression.
Claim 5
Dependent Claim
74 words
The method according to claim 2 wherein, the forming step of said groups further includes a step of detecting whether plural signals which appear in said Boolean expression representing said corresponding portion appear in plural ones of product terms within said Boolean expression; and, wherein said factorizing is omitted with respect to a signal which has been detected as one which appears only in one of the plural product terms within said Boolean expression.
Claim 6
Dependent Claim
105 words
The method according to claim 1 wherein, the predetermined delay time is expressed in terms of a total number of logic gate stages; the delay time of each logic circuit expressed by a Boolean expression is measured in terms of a total number of logic gate stages along which a signal passes from an input to an output within a logic circuit which will be obtained in each logic circuit is realized by the logic gates of said predetermined kinds; and the delay time of each combination is measured as a sum of logic gate stages measured for logic circuits which belongs to each combination.
Claim 7
Dependent Claim
127 words
The method according to claim 1, further including the steps of: copying, in a situation where a delay time of any of the combinations is larger than the predetermined delay time, at least one Boolean expression representing one of said plurality of said portions into another Boolean expression representing another of said portions, so as to form a new Boolean expression comprised of a combination of said copied Boolean expression and said another Boolean expression, as a new Boolean expression representing a new enlarged portion to be used instead of said another portion; and executing the forming step of said groups to the selecting step of a new digital logic circuit which includes the new portion represented by said new Boolean expression, instead of said another portion.
Claim 8
Dependent Claim
28 words
The method according to claim 1, wherein one of the selected combinations has a delay time which is greater than a delay time of the digital logic circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-14 | 1997-08-16 | 1998-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-14 | 2001-08-16 | 2002-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-14 | 2005-08-16 | 2006-02-15 | $7700.00 | Window Closed / Lapsed |