US5646545A
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Time multiplexed programmable logic device
Assignee: Xilinx Inc
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Filing: 1995-08-18
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Granted: 1997-07-08
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Expires: 2015-08-18
Abstract
Abstract A programmable logic device (PLD) comprises a plurality of configurable logic blocks (CLBs), an interconnect structure for interconnecting the CLBs, and a plurality of programmable logic elements for configuring the CLBs and the interconnect structure. Each CLB includes a combinational element and a sequential logic element, wherein at least one programmable logic element includes a plurality of memory cells for configuring the combinational element and at least one programmable logic element includes a plurality of memory cells for configuring the sequential logic element. A micro register, which stores a plurality of intermediate states of one CLB or interconnect structure, is located at the output of a CLB, the input of a CLB, or elsewhere in the interconnect structure. The PLD includes means for disabling access to at least one of said plurality of memory elements. In one embodiment, the memory cells are RAM cells, whereas in other embodiments the memory cells are ROM cells, or a combination thereof. The PLD switches between configurations sequentially, by random access, or on command from an external or internal signal. This reconfiguration allows the PLD to function in one of N configurations, wherein N is equal to the maximum number of memory cells assigned to each programmable point. In this manner, a PLD with a number M of actual CLBs functions as if it includes M times N effective CLBs.
Inventors
- 👤 Stephen M. Trimberger
- 👤 Richard A. Carberry
- 👤 Robert Anders Johnson
- 👤 Jennifer Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:03
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/1776; G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7867; G06F30/00; G06F30/30; G06F30/34; H03K19/17704
Claims Analysis
Total Claims: 79
Claim 1
Independent Claim
93 words
A programable logic device comprising: at least one configurable logic block, wherein each configurable logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least one configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programable logic element includes a plurality of memory cells for configuring said combinational element and at least one programable logic element includes a plurality of memory cells for configuring said sequential logic element.
Claim 2
Dependent Claim
93 words
A programable logic device comprising: at least one configurable logic block, wherein each configurable logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least one configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programable logic element includes a plurality of memory cells for configuring said combinational element and at least one programable logic element includes a plurality of memory cells for configuring said sequential logic element.
Claim 3
Dependent Claim
36 words
The programmable logic device of claim 1 further including a storage device for storing a plurality of intermediate logic states of one of the following: one configurable logic block and a portion of said interconnect structure.
Claim 4
Dependent Claim
28 words
The programmable logic device of claim 2 wherein each configurable logic block further includes a plurality of selectors for accessing signals in at least one configurable logic block.
Claim 5
Dependent Claim
23 words
The programable logic device of claim 2 wherein each configurable logic block further includes a plurality of selectors for accessing said intermediate states.
Claim 6
Dependent Claim
28 words
The programable logic device of claim 2 wherein each configurable logic block further includes a plurality of selectors for accessing signals in at least one configurable logic block.
Claim 7
Dependent Claim
17 words
The programmable logic device of claim 5 wherein said signals are output signals of sequential logic elements.
Claim 8
Dependent Claim
16 words
The programmable logic device of claim 5 wherein said signals are output signals of combinational elements.
Claim 9
Dependent Claim
24 words
The programmable logic device of claim 2 wherein each configurable logic block further includes a plurality of selectors for accessing said intermediate logic states.
Claim 10
Dependent Claim
22 words
The programmable logic device of claim 8 wherein said plurality of selectors further access signals in at least one configurable logic block.
Claim 11
Dependent Claim
18 words
The programmable logic device of claim 2 wherein said storage device is controlled by a first trigger signal.
Claim 12
Dependent Claim
18 words
The programmable logic device of claim 3 wherein said selectors are controlled by a plurality of trigger signals.
Claim 13
Dependent Claim
56 words
The programmable logic device of claim 2 further including a plurality of latches, wherein each bit of said storage device is provided to an associated latch, wherein the output terminals of said plurality of latches are coupled to the input terminals of a multiplexer, wherein said multiplexer is controlled by said plurality of programmable logic elements.
Claim 14
Dependent Claim
19 words
The programmable logic device of claim 12 wherein said plurality of latches are clocked by a first trigger signal.
Claim 15
Dependent Claim
28 words
The programmable logic device of claim 13 wherein said storage device is controlled by a plurality of trigger signals having a lower precision than said first trigger signal.
Claim 16
Dependent Claim
36 words
The programmable logic device of claim 13 further including a bypass latch coupled between said configurable logic block and said multiplexer, wherein said bypass latch is controlled by the same trigger as said plurality of latches.
Claim 17
Dependent Claim
26 words
The programmable logic device of claim 5 wherein each selector includes a first multiplexer for receiving signals from said configurable logic block and said storage device.
Claim 18
Dependent Claim
77 words
The programmable logic device of claim 16 further including: a second multiplexer for receiving signals from said first multiplexer, wherein said first multiplexer and said second multiplexer are controlled by a plurality of memory cells; and a plurality of latches, wherein a first latch receives signals from said first multiplexer and provides signals to said second multiplexer, and a second latch receives signals from said plurality of memory cells and provides control signals to said second multiplexer.
Claim 19
Dependent Claim
20 words
The programmable logic device of claim 16 wherein said storage device is clocked by a plurality of low precision clocks.
Claim 20
Dependent Claim
36 words
The programmable logic device of claim 2 further including a multiplexer in at least one configurable logic block for selectively providing a signal from the sequential logic element or the combinational element to said storage device.
Claim 21
Dependent Claim
24 words
The programmable logic device of claim 2 wherein each configurable logic block further includes an output multiplexer for receiving signals from said storage device.
Claim 22
Dependent Claim
20 words
The programmable logic device of claim 20 wherein said output multiplexer further receives bypass signals which bypass said storage device.
Claim 23
Dependent Claim
17 words
The programmable logic device of claim 21 wherein said signals are external to said configurable logic block.
Claim 24
Dependent Claim
17 words
The programmable logic device of claim 21 wherein said signals are internal to said configurable logic block.
Claim 25
Dependent Claim
26 words
The programmable logic device of claim 2 wherein said storage device is coupled to the input terminal of at least one of said configurable logic blocks.
Claim 26
Dependent Claim
16 words
The programmable logic device of claim 1 wherein said plurality of memory cells include RAM cells.
Claim 27
Dependent Claim
16 words
The programmable logic device of claim 1 wherein said plurality of memory cells include ROM cells.
Claim 28
Dependent Claim
47 words
The programmable logic device of claim 2 wherein a first configurable logic block includes a first output multiplexer block associated with a first storage device, wherein an output terminal of said first output multiplexer block is coupled to an input terminal of said first configurable logic block.
Claim 29
Dependent Claim
65 words
The programmable logic device of claim 2 wherein a first configurable logic block includes a first output multiplexer block associated with a first storage device, and a second configurable logic block includes a second output multiplexer block associated with a second storage device, wherein an output terminal of said first output multiplexer block is coupled to an input terminal of said second configurable logic block.
Claim 30
Dependent Claim
48 words
The programmable logic device of claim 2 wherein a first configurable logic block includes a first output multiplexer block associated with a first storage device, wherein an output terminal of said first output multiplexer block is selectively coupled to an input terminal of said first configurable logic block.
Claim 31
Dependent Claim
36 words
The programmable logic device of claim 2 wherein a first configurable logic block includes a first storage device, wherein said first storage device is selectively coupled to an input terminal of said first configurable logic block.
Claim 32
Dependent Claim
48 words
The programmable logic device of claim 2 wherein a first configurable logic block includes a first output multiplexer block associated with a first storage device, wherein an output terminal of said first output multiplexer block is selectively coupled to an input terminal of a second configurable logic block.
Claim 33
Dependent Claim
46 words
The programmable logic device of claim 1 further comprising a structure for coupling said plurality of memory cells to said at least one configurable logic block and said interconnect, wherein said structure includes a local bus interconnecting a first set of said plurality of memory cells.
Claim 34
Dependent Claim
138 words
A programmable logic device comprising: at least one configurable logic block, wherein each configurable logic block includes a combinational element and a sequentially logic element; an interconnect structure for interconnecting said at least one configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element and at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element; a structure for coupling said plurality of memory cells to said at least one configurable logic block and said interconnect, wherein said structure includes a local bus interconnecting a first set of said plurality of memory cells; and global bus connectable to said local bus.
Claim 35
Dependent Claim
138 words
A programmable logic device comprising: at least one configurable logic block, wherein each configurable logic block includes a combinational element and a sequentially logic element; an interconnect structure for interconnecting said at least one configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element and at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element; a structure for coupling said plurality of memory cells to said at least one configurable logic block and said interconnect, wherein said structure includes a local bus interconnecting a first set of said plurality of memory cells; and global bus connectable to said local bus.
Claim 36
Dependent Claim
20 words
The programmable logic device of claim 33 further including a switch for connecting said global bus to said local bus.
Claim 37
Dependent Claim
13 words
The programmable logic device of claim 34 wherein said switch includes a transistor.
Claim 38
Dependent Claim
14 words
The programmable logic device of claim 34 wherein said switch includes a buffered switch.
Claim 39
Dependent Claim
20 words
The programmable logic device of claim 1 further including a plurality of lines for accessing said plurality of memory cells.
Claim 40
Dependent Claim
26 words
The programmable logic device of claim 37 further including means for selecting a predetermined set of said plurality of programmable logic elements associated with one configuration.
Claim 41
Dependent Claim
16 words
The programmable logic device of claim 38 wherein said means for selecting includes a logic gate.
Claim 42
Dependent Claim
23 words
The programmable logic device of claim 34 wherein said plurality of programmable logic elements form an array of bit set columns and rows.
Claim 43
Dependent Claim
26 words
The programmable logic device of claim 40 wherein said means for coupling includes means for selectively accessing one of two bit set columns of said array.
Claim 44
Dependent Claim
19 words
The programmable logic device of claim 41 wherein said means for selectively accessing includes a first plurality of switches.
Claim 45
Dependent Claim
19 words
The programmable logic device of claim 42 wherein said means for selectively accessing includes a first plurality of transistors.
Claim 46
Dependent Claim
23 words
The programmable logic device of claim 40 wherein said means for coupling includes means for selecting one of a subset of said rows.
Claim 47
Dependent Claim
18 words
The programmable logic device of claim 44 wherein said means for selecting includes a first plurality of switches.
Claim 48
Dependent Claim
32 words
The programmable logic device of claim 45 wherein said means for coupling includes a second plurality of switches for coupling one of a subset of rows to one of said global lines.
Claim 49
Dependent Claim
38 words
The programmable logic device of claim 1 wherein the number of said plurality of memory cells in at least one programmable logic element differs from the number of said plurality of memory cells in another programmable logic element.
Claim 50
Dependent Claim
18 words
The programmable logic device of claim 1 wherein each programmable logic element includes a plurality of memory cells.
Claim 51
Dependent Claim
25 words
The programmable logic device of claim 2 further including means for recirculating an intermediate value stored in said storage device to a sequential logic element.
Claim 52
Dependent Claim
16 words
The programmable logic device of claim 2 wherein said storage device includes a single-bit storage device.
Claim 53
Dependent Claim
16 words
The programmable logic device of claim 2 wherein said storage device includes a multiple-bit storage device.
Claim 54
Dependent Claim
15 words
The programmable logic device of claim 51 wherein said storage device includes a shift register.
Claim 55
Dependent Claim
43 words
The programmable logic device of claim 2 wherein at least one combinational logic block further includes a multiplexer for selectively providing a signal from said combinational element, an external signal of said combinational logic block, or a signal from said sequential logic element.
Claim 56
Dependent Claim
109 words
A programmable logic device comprising: at least one configurable logic block, wherein each configure logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least one configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element and at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element, wherein at least one combinational logic element includes means for time multiplexing its logic input signals.
Claim 57
Dependent Claim
109 words
A programmable logic device comprising: at least one configurable logic block, wherein each configure logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least one configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element and at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element, wherein at least one combinational logic element includes means for time multiplexing its logic input signals.
Claim 58
Dependent Claim
110 words
A programmable logic device comprising: at least one configure block logic block, wherein each configurable logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least one configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element and at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element, wherein at least one sequential logic element includes means for time multiplexing its logic input signals.
Claim 59
Dependent Claim
110 words
A programmable logic device comprising: at least one configure block logic block, wherein each configurable logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least one configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element and at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element, wherein at least one sequential logic element includes means for time multiplexing its logic input signals.
Claim 60
Dependent Claim
109 words
A programmable logic device comprising; at least one configurable logic block, wherein each configurable logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least one configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element and at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element, wherein at least one combinational logic element includes means for time multiplexing its configuration input signals.
Claim 61
Dependent Claim
109 words
A programmable logic device comprising; at least one configurable logic block, wherein each configurable logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least one configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element and at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element, wherein at least one combinational logic element includes means for time multiplexing its configuration input signals.
Claim 62
Dependent Claim
108 words
A programmable logic device comprising: at least one configurable logic block, wherein each configurable logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least one configurable logic block; plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element and at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element, wherein at least one sequential logic element includes means for time multiplexing its configuration input signals.
Claim 63
Dependent Claim
108 words
A programmable logic device comprising: at least one configurable logic block, wherein each configurable logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least one configurable logic block; plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element and at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element, wherein at least one sequential logic element includes means for time multiplexing its configuration input signals.
Claim 64
Dependent Claim
78 words
A programmable logic device comprising: a configurable logic block including a combinational element and a sequential logic element; an input/output block; an interconnect structure for interconnecting said configurable logic block and said input/output block; a plurality of programmable logic elements for configuring said configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells; and a storage device for storing a plurality of intermediate states of said input/output block.
Claim 65
Dependent Claim
78 words
A programmable logic device comprising: a configurable logic block including a combinational element and a sequential logic element; an input/output block; an interconnect structure for interconnecting said configurable logic block and said input/output block; a plurality of programmable logic elements for configuring said configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells; and a storage device for storing a plurality of intermediate states of said input/output block.
Claim 66
Dependent Claim
63 words
A programmable logic device comprising: at least one configurable element; an interconnect structure for interconnecting said at least one configurable element; and a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes at least one ROM cell and at said one programmable cell for configuring said at least one configurable element.
Claim 67
Dependent Claim
63 words
A programmable logic device comprising: at least one configurable element; an interconnect structure for interconnecting said at least one configurable element; and a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes at least one ROM cell and at said one programmable cell for configuring said at least one configurable element.
Claim 68
Dependent Claim
82 words
A programable logic device comprising: at least one configurable element; an interconnect structure for interconnecting said at least one configurable element; a plurality of programable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells for configuring said at least one configurable element; and a latch for providing a value of one of said plurality of memory cells as an output signal of one of said programmable logic elements.
Claim 69
Dependent Claim
82 words
A programable logic device comprising: at least one configurable element; an interconnect structure for interconnecting said at least one configurable element; a plurality of programable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells for configuring said at least one configurable element; and a latch for providing a value of one of said plurality of memory cells as an output signal of one of said programmable logic elements.
Claim 70
Dependent Claim
87 words
A programmable logic device comprising: at least one configurable element; an interconnect structure for interconnecting said at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells for configuring said at least one configurable element, wherein the number of said plurality of memory cells in a first programmable logic element differs from the number of said plurality of memory cells in a second programmable logic element.
Claim 71
Dependent Claim
87 words
A programmable logic device comprising: at least one configurable element; an interconnect structure for interconnecting said at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells for configuring said at least one configurable element, wherein the number of said plurality of memory cells in a first programmable logic element differs from the number of said plurality of memory cells in a second programmable logic element.
Claim 72
Dependent Claim
119 words
A programmable logic device comprising: at least one configurable logic block, wherein each configurable logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least one configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element and at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element; and a latch for providing a value of one of said plurality of memory cells as an output signal of one of said programmable logic elements.
Claim 73
Dependent Claim
119 words
A programmable logic device comprising: at least one configurable logic block, wherein each configurable logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least one configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element and at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element; and a latch for providing a value of one of said plurality of memory cells as an output signal of one of said programmable logic elements.
Claim 74
Dependent Claim
103 words
A programmable logic device comprising: at least one configurable logic block, wherein each configurable logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element, at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element, and at least one of said configurable logic blocks includes look-up tables.
Claim 75
Dependent Claim
103 words
A programmable logic device comprising: at least one configurable logic block, wherein each configurable logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element, at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element, and at least one of said configurable logic blocks includes look-up tables.
Claim 76
Dependent Claim
128 words
A programmable logic device including: at least one configurable logic block, wherein each configurable logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least one configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element and at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element; a plurality of lines for accessing said plurality of memory cells; and a register for selecting a predetermined set of said plurality of programmable logic elements associated with one configuration within one configurable logic block.
Claim 77
Dependent Claim
128 words
A programmable logic device including: at least one configurable logic block, wherein each configurable logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least one configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element and at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element; a plurality of lines for accessing said plurality of memory cells; and a register for selecting a predetermined set of said plurality of programmable logic elements associated with one configuration within one configurable logic block.
Claim 78
Dependent Claim
116 words
A programmable logic device comprising: at least one configurable logic block, wherein each configurable logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least one configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element and at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element, wherein said at least one programmable logic element includes means for disabling access to at least one of said plurality of memory elements.
Claim 79
Dependent Claim
116 words
A programmable logic device comprising: at least one configurable logic block, wherein each configurable logic block includes a combinational element and a sequential logic element; an interconnect structure for interconnecting said at least one configurable logic block; a plurality of programmable logic elements for configuring said at least one configurable logic block and said interconnect structure, wherein at least one programmable logic element includes a plurality of memory cells for configuring said combinational element and at least one programmable logic element includes a plurality of memory cells for configuring said sequential logic element, wherein said at least one programmable logic element includes means for disabling access to at least one of said plurality of memory elements.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-07 | 2001-01-06 | 2001-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-07 | 2005-01-06 | 2005-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-07 | 2009-01-06 | 2009-07-08 | $7700.00 | Window Closed / Lapsed |