US3775756A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable special purpose processor having simultaneous execution and instruction and data access
Assignee: General Electric Co
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Filing: 1972-07-20
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Granted: 1973-11-27
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Expires: 1992-07-20
Abstract
Abstract In a programmable special purpose processor for an input/output controller, data and data moving instructions are respectively stored in data and instruction memories rather than in one memory. While a data word is accessed from a data register to an arithmetic unit in response to a data moving instruction, an instruction counter is updated to direct the subsequent instruction to be delivered to an instruction register to prepare the processor to perform its next data moving operation. At the same time, in response to a data memory address register, a next data word is accessed from a data memory to the data register. At the beginning of the next cycle, the processor is prepared to execute the next instruction. Consequently, the processor operating speed is increased since data words and instructions need not be sequentially accessed during a cycle.
Inventors
- 👤 C Balser
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 11:19
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F9/3824; G06F9/3867; G06F9/3885; G06F9/3889
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
177 words
In a special purpose processor, a timing control and data path circuit for operating in synchronism with clocksignals comprising in combination: a data memory, a data register coupled to said data memory for storing a current data word, a data memory address register for storing an address indicative of a next data word stored in said memory and coupled for addressing said data memory, an instruction memory, an instruction counter coupled to address said instruction memory and providing an address indicative of a next instruction of a program, a data address generator coupled to the output of said instruction memory and coupled for providing a data address to said data memory address register indicative of a next data word, an instruction register coupled to said instruction memory for storing a current instruction, and an instruction decoder coupled to said instruction register for enabling said data register to provide the current word, whereby an instruction is executed simultaneously with accessing of a next instruction and a next data word from said instruction memory and said data memory respectively.
Claim 2
Dependent Claim
177 words
In a special purpose processor, a timing control and data path circuit for operating in synchronism with clocksignals comprising in combination: a data memory, a data register coupled to said data memory for storing a current data word, a data memory address register for storing an address indicative of a next data word stored in said memory and coupled for addressing said data memory, an instruction memory, an instruction counter coupled to address said instruction memory and providing an address indicative of a next instruction of a program, a data address generator coupled to the output of said instruction memory and coupled for providing a data address to said data memory address register indicative of a next data word, an instruction register coupled to said instruction memory for storing a current instruction, and an instruction decoder coupled to said instruction register for enabling said data register to provide the current word, whereby an instruction is executed simultaneously with accessing of a next instruction and a next data word from said instruction memory and said data memory respectively.
Claim 3
Dependent Claim
47 words
A timing control and data path circuit according to claim 1 further comprising a plus-one adder coupled from the output of said instruction counter to an input of said instruction counter for updating said instruction counter after said instruction counter providEs an address to said instruction memory.
Claim 4
Dependent Claim
63 words
A timing control and data path circuit according to claim 1 further comprising an early instruction decoder coupled to the output of said instruction memory and a branch vector generator coupled to the output of said early instruction decoder, said branch vector generator coupled to provide said instruction counter with a branch vector when the next instruction is indicative of a branch instruction.
Claim 5
Dependent Claim
47 words
A timing control and data path circuit according to claim 3 further comprising a plus-one adder coupled from the output of said instruction counter to an input of said instruction counter for updating said instruction counter after said instruction counter provides an address to said instruction memory.
Claim 6
Dependent Claim
24 words
A timing control and data path circuit according to claim 4 further comprising an arithmetic unit coupled to the output of said data register.
Claim 7
Dependent Claim
44 words
A timing control and data path circuit according to claim 5 in which said arithmetic unit is coupled to said branch vector generator for providing an indicator when the computation performed by said arithmetic unit is indicative of a result requiring a branch instruction.
Claim 8
Dependent Claim
35 words
A timing control and data path circuit according to claim 5 further comprising a data output gate coupled to said data memory, said data output gate also being coupled for enabling by said instruction decoder.
References Cited (Backward Citations)
US3629853A
Cited
US3344404A
Cited
US3404378A
Cited
US3431558A
Cited
US3470540A
Cited
US3537072A
Cited
US3599176A
Cited
US3623158A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-11-26 | 1977-05-28 | 1977-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-11-26 | 1981-05-28 | 1981-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-11-26 | 1985-05-28 | 1985-11-27 | $7700.00 | Window Closed / Lapsed |