Programmable special purpose processor having simultaneous execution and instruction and data access

Claim 1

In a special purpose processor, a timing control and data path circuit for operating in synchronism with clocksignals comprising in combination: a data memory, a data register coupled to said data memory for storing a current data word, a data memory address register for storing an address indicative of a next data word stored in said memory and coupled for addressing said data memory, an instruction memory, an instruction counter coupled to address said instruction memory and providing an address indicative of a next instruction of a program, a data address generator coupled to the output of said instruction memory and coupled for providing a data address to said data memory address register indicative of a next data word, an instruction register coupled to said instruction memory for storing a current instruction, and an instruction decoder coupled to said instruction register for enabling said data register to provide the current word, whereby an instruction is executed simultaneously with accessing of a next instruction and a next data word from said instruction memory and said data memory respectively.