Planarization method and system using variable exposure

Claim 2

A process for planarizing a contoured topographic surface of a semiconductor wafer comprising the steps of: applying a resist to said contoured topographic surface, said resist having a topographical contour substantially matching the contour of said contoured topographic surface; exposing selected portions of said resist on said contoured topographic surface to radiation through a variable density pattern mask, said variable density pattern mask having a plurality of densities relating to said topographical contour of said resist; and developing said resist and leaving a developed resist layer with a substantially planar surface.

Claim 3

The process according to claim 1 , wherein said resist topographical contour has hills and valleys, said resist is a positive resist, and during the step of exposing, less dense ones of said plurality of densities are aligned with said hills and more dense ones of said plurality of densities are aligned with said valleys.

Claim 4

The process according to claim 1 , wherein said resist topographical contour has hills and valleys, said resist is a negative resist, and during the step of exposing, more dense ones of said plurality of densities are aligned with said hills and less dense ones of said plurality of densities are aligned with said valleys.

Claim 5

A process for planarizing a surface of a semiconductor wafer which includes at least one feature and a uniform thickness resist layer coating said surface, said resist layer coating having a contoured topography in response to coating said at least one feature on said wafer, said process including the step of: exposing said resist through a mask having patterns relating to said contoured topography and said at least one feature, so that when developed the resist layer varies in thickness so as to compensate for a topography of said at least one feature, leaving a developed resist layer with a substantially planar surface.

Claim 6

A process for planarizing a surface of a semiconductor wafer which includes at least one feature and a uniform thickness resist layer coating said surface, said resist layer coating having a contoured topography in response to coating said at least one feature on said wafer, said process including the step of: exposing said resist through a mask having patterns relating to said contoured topography and said at least one feature, so that when developed the resist layer varies in thickness so as to compensate for a topography of said at least one feature, leaving a developed resist layer with a substantially planar surface.

Claim 7

The process according to claim 4 , wherein said resist is a positive resist, and said mask patterns are proportionally related to said contoured topography and said at least one feature.

Claim 8

The process according to claim 4 , wherein said resist is a negative resist, and said mask patterns are inversely related to said contoured topography and said at least one feature.

Claim 9

A process for planarizing a surface of a semiconductor wafer which includes a first region with multiple deep trenches and a second region apart from said first region, said wafer including a coated resist layer whose thickness is greater over said second region than over said first region, said process including the step of: exposing said first region with radiation of a first intensity and exposing said second region with radiation of a second intensity through a variable density pattern mask, said first intensity being related to said thickness of the resist layer in said first region, said second intensity being related to said thickness of the resist layer in said second region, so that when developed said resist layer has a uniform height over said first and second regions.

Claim 10

A process for planarizing a surface of a semiconductor wafer which includes a first region with multiple deep trenches and a second region apart from said first region, said wafer including a coated resist layer whose thickness is greater over said second region than over said first region, said process including the step of: exposing said first region with radiation of a first intensity and exposing said second region with radiation of a second intensity through a variable density pattern mask, said first intensity being related to said thickness of the resist layer in said first region, said second intensity being related to said thickness of the resist layer in said second region, so that when developed said resist layer has a uniform height over said first and second regions.

Claim 11

A process according to claim 7 , said exposing step exposing said first and second regions so that said resist overlying said second region is removed and said resist overlying said first region is removed at least to the tops of the multiple deep trenches.

Claim 12

The process according to claim 7 , wherein said resist is a positive resist, said first intensity being proportionally related to thickness of said resist layer in, and said second intensity being proportionally related to thickness of said resist layer in said second region.

Claim 13

The process according to claim 7 , wherein said resist is a negative resist, said mask being inversely related to thickness of said resist layer in said first region, and said second intensity being inversely related to thickness of said resist layer in said second region.

Claim 14

A process for planarizing a surface of a semiconductor wafer which includes a first region with multiple deep trenches and a second region apart from said first region, said process including the steps of: coating said wafer with a resist layer whose thickness is greater over said second region than over said first region; aligning a mask with the resist layer, the mask having a variable density pattern having densities related to said thicknesses of the resist layer in said first and second regions; and exposing said first region with radiation of a first intensity and exposing said second region with radiation of a second intensity through the variable density pattern mask, so that when developed said resist layer has a uniform height over said first and second regions.

Claim 15

A process for planarizing a surface of a semiconductor wafer which includes a first region with multiple deep trenches and a second region apart from said first region, said process including the steps of: coating said wafer with a resist layer whose thickness is greater over said second region than over said first region; aligning a mask with the resist layer, the mask having a variable density pattern having densities related to said thicknesses of the resist layer in said first and second regions; and exposing said first region with radiation of a first intensity and exposing said second region with radiation of a second intensity through the variable density pattern mask, so that when developed said resist layer has a uniform height over said first and second regions.

Claim 16

The process according to claim 11 , wherein in said exposing step the process further comprises exposing said first and second regions so that said resist overlying said second region is removed and said resist overlying said first region is removed at least to the tops of the multiple deep trenches.

Claim 17

The process according to claim 11 , wherein said resist is a positive resist and said pattern densities are arranged to directly relate to said resist layer thicknesses.

Claim 18

The process according to claim 11 wherein said resist is a negative resist and said pattern densities are arranged to inversely relate to said resist layer thicknesses.