Patent US6432787B1 successfully refreshed from Google Patents.
US6432787B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for providing low-GIDL dual workfunction gate doping with borderless diffusion contact
Assignee: GlobalFoundries Inc
•
Filing: 2001-10-22
•
Granted: 2002-08-13
•
Expires: 2021-10-22
Abstract
Abstract A semiconductor structure is provided along with a corresponding method of producing such a structure. The method and structure may include providing a semiconductor substrate, a gate insulator over the semiconductor substrate, a conductor comprising intrinsic polysilicon over the gate insulator, a silicide layer over the polysilicon and an insulating cap over the silicide layer. Insulating spacers may be provided along sides of the silicide layer and the insulating cap. The polysilicon may be doped with a first conductive type dopant. The first conductive type dopant may be spread over the polysilicon to form a doped polysilicon layer. A gate sidewall layer may be formed on sides of the doped polysilicon layer. A bird's beak of the gate sidewall layer may also be formed in a corner of the polysilicon.
Inventors
- 👤 Jack A. Mandelman
- 👤 Ramachandra Divakaruni
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:57
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/09; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D84/014; H10D84/0147; H10D84/02; H10D84/03; H10D84/038; H10B12/02; H10B12/05
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
83 words
A method for forming a semiconductor structure comprising: providing a semiconductor wafer having a first region comprising first features, said first features being separated by a first spacing approximately equal to a minimum width, said semiconductor wafer further comprising a second region including second features having second feature sidewalls, said second features being separated by a second spacing; forming dielectric spacers on said sidewalls leaving exposed horizontal surfaces in said second region; and selectively etching said exposed horizontal surfaces in said second region.
Claim 2
Independent Claim
83 words
A method for forming a semiconductor structure comprising: providing a semiconductor wafer having a first region comprising first features, said first features being separated by a first spacing approximately equal to a minimum width, said semiconductor wafer further comprising a second region including second features having second feature sidewalls, said second features being separated by a second spacing; forming dielectric spacers on said sidewalls leaving exposed horizontal surfaces in said second region; and selectively etching said exposed horizontal surfaces in said second region.
Claim 3
Dependent Claim
22 words
The method of claim 1 , wherein said first region comprises an array region and said second region comprises a support region.
Claim 4
Dependent Claim
16 words
The method of claim 1 , wherein said first features include a partial gate conductor stack.
Claim 5
Dependent Claim
22 words
The method of claim 3 , wherein said partial gate conductor stack comprises a tungsten silicide layer and a silicon nitride cap.
Claim 6
Dependent Claim
53 words
The method of claim 3 , wherein said first feature includes sidewalls, and the method further comprises: implanting a first dopant in exposed horizontal surfaces of a semiconductive layer in said first region; and spreading said first dopant within said semiconductive layer to form a first doped semiconductive layer underlying said first features.
Claim 7
Dependent Claim
26 words
The method of claim 5 , wherein said first dopant is selected from the group consisting of an N type dopant and a P type dopant.
Claim 8
Dependent Claim
14 words
The method of claim 5 , wherein said spreading comprises a rapid thermal anneal.
Claim 9
Dependent Claim
26 words
The method of claim 5 , further comprising anisotropically etching said first doped semiconductive layer to form a full gate conductor stack in said first region.
Claim 10
Independent Claim
158 words
A method for forming a semiconductor structure comprising: providing a semiconductor wafer having a first region comprising first features, said first features being separated by a first spacing approximately equal to a minimum width, said semiconductor wafer further comprising a second region including second features having second feature sidewalls, said second features being separated by a second spacing, said second spacing being larger than said minimum width; depositing a dielectric material over said semiconductor wafer, said dielectric material having a thickness such that said first spacing is substantially filled by said dielectric material and said dielectric material forms a layer conformally over and between said second features; anisotropically etching horizontal areas of said dielectric material so that said first spacing remains substantially filled with said dielectric material and so that spacers of said dielectric material remain on said sidewalls leaving exposed horizontal surfaces of said second region; and selectively etching said exposed horizontal surfaces in said second region.
Claim 11
Independent Claim
158 words
A method for forming a semiconductor structure comprising: providing a semiconductor wafer having a first region comprising first features, said first features being separated by a first spacing approximately equal to a minimum width, said semiconductor wafer further comprising a second region including second features having second feature sidewalls, said second features being separated by a second spacing, said second spacing being larger than said minimum width; depositing a dielectric material over said semiconductor wafer, said dielectric material having a thickness such that said first spacing is substantially filled by said dielectric material and said dielectric material forms a layer conformally over and between said second features; anisotropically etching horizontal areas of said dielectric material so that said first spacing remains substantially filled with said dielectric material and so that spacers of said dielectric material remain on said sidewalls leaving exposed horizontal surfaces of said second region; and selectively etching said exposed horizontal surfaces in said second region.
Claim 12
Dependent Claim
22 words
The method of claim 9 , wherein said first region comprises an array region and said second region comprises a support region.
Claim 13
Dependent Claim
16 words
The method of claim 9 , wherein said first features include a partial gate conductor stack.
Claim 14
Dependent Claim
22 words
The method of claim 11 , wherein said partial gate conductor stack comprises a tungsten silicide layer and a silicon nitride cap.
Claim 15
Independent Claim
201 words
A method of fabricating a semiconductor structure comprising: providing a substrate having a first region and a second region; depositing a gate dielectric layer over said substrate in said first region; depositing a semiconductive layer over said gate dielectric layer in said first region; forming a plurality of partial gate stacks over said semiconductive layer in said first region, wherein each of said partial gate stacks are separated by a first spacing approximately equal to a minimum width; forming a plurality of second features having second feature sidewalls in said second region, said second features being separated by a second spacing, said second spacing being larger than said minimum width; depositing a dielectric material over said semiconductor wafer, said dielectric material having a thickness such that said first spacing is substantially filled by said dielectric material and said dielectric material forms a layer conformally over and between said second features; anisotropically etching horizontal areas of said dielectric material so that said first spacing remains substantially filled with said dielectric material and so that spacers of said dielectric material remain on said sidewalls leaving exposed horizontal surfaces of said second region; and selectively etching said exposed horizontal surfaces in said second region.
Claim 16
Independent Claim
201 words
A method of fabricating a semiconductor structure comprising: providing a substrate having a first region and a second region; depositing a gate dielectric layer over said substrate in said first region; depositing a semiconductive layer over said gate dielectric layer in said first region; forming a plurality of partial gate stacks over said semiconductive layer in said first region, wherein each of said partial gate stacks are separated by a first spacing approximately equal to a minimum width; forming a plurality of second features having second feature sidewalls in said second region, said second features being separated by a second spacing, said second spacing being larger than said minimum width; depositing a dielectric material over said semiconductor wafer, said dielectric material having a thickness such that said first spacing is substantially filled by said dielectric material and said dielectric material forms a layer conformally over and between said second features; anisotropically etching horizontal areas of said dielectric material so that said first spacing remains substantially filled with said dielectric material and so that spacers of said dielectric material remain on said sidewalls leaving exposed horizontal surfaces of said second region; and selectively etching said exposed horizontal surfaces in said second region.
Claim 17
Dependent Claim
48 words
The method of claim 13 , wherein the forming of a plurality of partial gate stacks further comprises: depositing a tungsten silicide layer; depositing a silicon nitride layer; and patterning and etching through said nitride layer and said tungsten silicide layer down to at least said semiconductive layer.
Claim 18
Dependent Claim
12 words
The method of claim 14 , wherein said semiconductive layer comprises polysilicon.
Claim 19
Dependent Claim
81 words
The method of claim 14 , wherein said first feature includes sidewalls, and the method further comprises: removing said dielectric material to expose said first feature sidewalls and horizontal surfaces of said semiconductive layer in said first region; forming spacers on said first feature sidewalls; implanting a first dopant in exposed horizontal surfaces of said semiconductive layer in said first region; and spreading said first dopant within said semiconductive layer to form a first doped semiconductive layer underlying said first features.
Claim 20
Dependent Claim
81 words
The method of claim 15 , wherein said first feature includes sidewalls, and the method further comprises: removing said dielectric material to expose said first feature sidewalls and horizontal surfaces of said semiconductive layer in said first region; forming spacers on said first feature sidewalls; implanting a first dopant in exposed horizontal surfaces of said semiconductive layer in said first region; and spreading said first dopant within said semiconductive layer to form a first doped semiconductive layer underlying said first features.
Claim 21
Dependent Claim
26 words
The method of claim 17 , wherein said first dopant is selected from the group consisting of an N type dopant and a P type dopant.
Claim 22
Dependent Claim
14 words
The method of claim 17 , wherein said spreading comprises a rapid thermal anneal.
Claim 23
Dependent Claim
26 words
The method of claim 17 , further comprising anisotropically etching said first doped semiconductive layer to form a full gate conductor stack in said first region.
References Cited (Backward Citations)
US5424572A
Cited
US5213990A
Cited
US5589415A
Cited
US6284633B1
Cited
US6171959B1
Cited
US6277758B1
Cited
US6362055B2
Cited
US6346442B1
Cited
US6281559B1
Cited
US6342452B1
Cited
US6274467B1
Cited
US6281064B1
Cited
US6288419B1
Cited
US6200834B1
Cited
US6337246B1
Cited
US6281084B1
Cited
US6235584B1
Cited
US6153486A
Cited
US6333244B1
Cited
US6326260B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-08-12 | 2006-02-11 | 2006-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-08-12 | 2010-02-11 | 2010-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-08-12 | 2014-02-11 | 2014-08-13 | $7700.00 | Window Closed / Lapsed |