US6426252B1 — Silicon-on-insulator vertical array DRAM cell wit…

Claim 1

Independent Claim 101 words

A method of forming a memory cell in a layered semiconductor wafer, said layered semiconductor wafer including a buried dielectric layer, said method comprising the steps of: a) forming a trench capacitor in a layered semiconductor wafer; b) forming a conductive strap in a buried dielectric layer from a plate of said trench capacitor to a bottom surface of a top semiconductor layer of said layered semiconductor wafer; c) forming a vertical transistor along a sidewall of said top semiconductor layer; and d) forming semiconductor islands of said top semiconductor layer, said vertical transistor being on one of said semiconductor islands.

Claim 2

Independent Claim 101 words

A method of forming a memory cell in a layered semiconductor wafer, said layered semiconductor wafer including a buried dielectric layer, said method comprising the steps of: a) forming a trench capacitor in a layered semiconductor wafer; b) forming a conductive strap in a buried dielectric layer from a plate of said trench capacitor to a bottom surface of a top semiconductor layer of said layered semiconductor wafer; c) forming a vertical transistor along a sidewall of said top semiconductor layer; and d) forming semiconductor islands of said top semiconductor layer, said vertical transistor being on one of said semiconductor islands.

Claim 3

Dependent Claim 86 words

A method as in claim 1 , wherein the layered semiconductor wafer is a silicon wafer, the buried dielectric layer is a buried oxide (BOX) layer and the step (a) of forming a trench capacitor comprises the steps of: i) forming first trenches in said top silicon layer, said BOX layer and into said substrate; ii) forming a dielectric layer on said substrate and in said trenches; and iii) filling said trenches with polysilicon to a point in said BOX layer below said top silicon layer.

Claim 4

Dependent Claim 66 words

A method as in claim 2 , wherein the step (i) of forming the first trenches comprises the steps of: A) forming a protective pad layer on said top silicon layer; B) forming a hard mask pattern on said protective pad layer to define said first trenches; and C) etching said first trenches through the top silicon layer, the BOX layer and into the silicon substrate.

Claim 5

Dependent Claim 81 words

A method as in claim 1 , wherein the layered semiconductor wafer is a silicon wafer, the buried dielectric layer is a buried oxide (BOX) layer and the step (b) of forming the conductive strap comprises the steps of: i) forming recess areas in the BOX layer sidewalls of said first trenches, said recesses being bounded on the top by said top silicon layer and on one side by said capacitor plates; and ii) filling said recess areas with doped polysilicon.

Claim 6

Dependent Claim 55 words

A method as in claim 4 , wherein the step (ii) of filling the recesses comprises the steps of: A) depositing a conformal layer of polysilicon; and B) selectively etching said polysilicon layer, straps remaining in said recess areas and in contact with said capacitor plates and a bottom surface of said top silicon layer.

Claim 7

Dependent Claim 26 words

A method as in claim 4 , wherein the step (i) of forming recess areas further includes forming an oxidation of nitride on exposed silicon surfaces.

Claim 8

Dependent Claim 126 words

A method as in claim 1 , wherein the layered semiconductor wafer is a silicon wafer, the buried dielectric layer is a buried oxide (BOX) layer, the conductive gate material is polysilicon and the step (c) of forming the vertical transistors comprises: i) forming a trench top oxide (TTO) layer on said capacitor plates, a top of said TTO layer being below a top surface of said top silicon layer; ii) filling said trenches above said TTO layer with polysilicon, said polysilicon extending along trench sidewalls between said TTO layer and said top surface; and iii) forming a diffusion layer of a first dopant type in said top surface, dopant of said first dopant type outdiffusing from said conductive straps and forming a buried source diffusion.

Claim 9

Dependent Claim 61 words

A method as in claim 1 , wherein the layered semiconductor wafer is a silicon wafer, the buried dielectric layer is a buried oxide (BOX) layer and the step (d) of forming semiconductor islands comprises: i) forming a plurality of second trenches through said top silicon layer and said buried oxide layer; and ii) filling said second trenches with insulating material.

Claim 10

Dependent Claim 68 words

A method of forming an array of memory cells as in claim 1 , wherein the layered semiconductor wafer is a silicon wafer, the buried dielectric layer is a buried oxide (BOX) layer, the method further comprising: e) forming wordlines connected to gates of a plurality of said vertical transistors; and f) forming a plurality of bitlines connected to bitline diffusions of a plurality of said vertical transistors.

Claim 11

Independent Claim 132 words

A method of forming a,dynamic random access memory (DRAM), including an array of trench capacitor memory cells, said trench capacitor memory cells being formed in a layered silicon wafer, said layered silicon wafer including a buried oxide layer isolating a substrate from a surface silicon layer, said method comprising the steps of: a) forming trench capacitors in a substrate of a layered silicon wafer; b) forming conductive straps in a buried oxide (BOX) layer above said substrate from said trench capacitors to a bottom surface of a top silicon layer, said top silicon layer being above said BOX layer; c) forming vertical transistors along a sidewall of said top silicon layer; and d) forming silicon islands of said top silicon layer, said vertical transistors each being on one of said silicon islands.

Claim 12

Independent Claim 132 words

A method of forming a,dynamic random access memory (DRAM), including an array of trench capacitor memory cells, said trench capacitor memory cells being formed in a layered silicon wafer, said layered silicon wafer including a buried oxide layer isolating a substrate from a surface silicon layer, said method comprising the steps of: a) forming trench capacitors in a substrate of a layered silicon wafer; b) forming conductive straps in a buried oxide (BOX) layer above said substrate from said trench capacitors to a bottom surface of a top silicon layer, said top silicon layer being above said BOX layer; c) forming vertical transistors along a sidewall of said top silicon layer; and d) forming silicon islands of said top silicon layer, said vertical transistors each being on one of said silicon islands.

Claim 13

Dependent Claim 70 words

A method of forming a DRAM as in claim 10 , wherein the step (a) of forming trench capacitors comprises the steps of: i) forming first trenches in said top silicon layer, said BOX layer and into said substrate; ii) forming a dielectric layer on said substrate and in said trenches; and iii) filling said trenches with polysilicon to a point in said BOX layer below said top silicon layer.

Claim 14

Dependent Claim 70 words

A method of forming a DRAM as in claim 11 , wherein the step (i) of forming the first trenches comprises the steps of: A) forming a protective pad layer on said top silicon layer; B) forming a hard mask pattern on said protective pad layer to define said first trenches; and C) etching said first trenches through the top silicon layer, the BOX layer and into the silicon substrate.

Claim 15

Dependent Claim 66 words

A method of forming a DRAM as in claim 11 , wherein the step (b) of forming the conductive strap comprises the steps of: i) forming recess areas in the BOX layer sidewalls of said first trenches, said recesses being bounded on the top by said top silicon layer and on one side by said capacitor plates; and ii) filling said recess areas with doped polysilicon.

Claim 16

Dependent Claim 55 words

A method as in claim 13 , wherein the step (ii) of filling the recesses comprises the steps of: A) depositing a conformal layer of polysilicon; and B) selectively etching said polysilicon layer, straps remaining in said recess areas and in contact with said capacitor plates and a bottom surface of said top silicon layer.

Claim 17

Dependent Claim 26 words

A method as in claim 13 , wherein the step (i) of forming recess areas further includes forming an oxidation of nitride on exposed silicon surfaces.

Claim 18

Dependent Claim 102 words

A method of forming a DRAM as in claim 11 , wherein the step (c) of forming the vertical transistors comprises: i) forming a trench top oxide (TTO) on said capacitor plates, a top surface of said TTO being below a top surface of said top silicon layer; ii) filling said trenches above said TTO with polysilicon, said polysilicon extending along trench sidewalls between said TTO and said top surface; and iii) forming a diffusion layer of a first dopant type in said top surface, dopant of said first dopant type outdiffusing from said conductive straps and forming a buried source diffusion.

Claim 19

Dependent Claim 45 words

A method of forming a DRAM as in claim 11 , wherein the step (d) of forming semiconductor islands comprises: i) forming a plurality of second trenches through said top silicon layer and said buried oxide layer; and ii) filling said second trenches with oxide.

Claim 20

Dependent Claim 48 words

A method of forming a DRAM as in claim 11 , wherein further comprising the steps of: e) forming wordlines connected to gates of a plurality of said vertical transistors; and f) forming a plurality of bitlines connected to bitline diffusions of a plurality of said vertical transistors.

Claim 21

Independent Claim 111 words

A method of forming memory cells comprising the steps of: a) forming a buried dielectric layer in a semiconductor wafer; b) etching first trenches through an upper surface layer of said semiconductor wafer through said buried dielectric layer and into a substrate beneath said buried dielectric layer; c) forming a capacitor plate in each of said first trenches within said substrate; d) recessing said buried dielectric layer within said first trenches; e) forming conductive straps in said recesses from said capacitor plates to said surface layer; f) implanting dopant into said semiconductor wafer; g) filling said first trenches with conductive gate material; and h) forming second trenches through said surface layer.

Claim 22

Independent Claim 111 words

A method of forming memory cells comprising the steps of: a) forming a buried dielectric layer in a semiconductor wafer; b) etching first trenches through an upper surface layer of said semiconductor wafer through said buried dielectric layer and into a substrate beneath said buried dielectric layer; c) forming a capacitor plate in each of said first trenches within said substrate; d) recessing said buried dielectric layer within said first trenches; e) forming conductive straps in said recesses from said capacitor plates to said surface layer; f) implanting dopant into said semiconductor wafer; g) filling said first trenches with conductive gate material; and h) forming second trenches through said surface layer.

Claim 23

Dependent Claim 53 words

The method of claim 19 , wherein the semiconductor wafer is a silicon wafer and the step (a) of forming the buried dielectric layer comprises implanting oxygen ions into the silicon wafer to form a buried oxide (BOX) layer isolating the silicon surface layer from a thicker silicon substrate beneath said BOX layer.

Claim 24

Dependent Claim 18 words

The method of claim 20 wherein the silicon surface layer is thickened after the BOX layer is formed.

Claim 25

Dependent Claim 63 words

The method of claim 20 , wherein the step (b) of etching the first trenches comprises-the steps of: i) forming a protective pad layer on said silicon layer; ii) forming a hard mask pattern on said protective pad layer to define said first trenches; iii) etching said first trenches through the silicon surface layer, the BOX layer and into the thicker silicon substrate.

Claim 26

Dependent Claim 25 words

The method of claim 22 , wherein before the step (i) a thermal oxide layer is grown on an upper surface of the silicon layer.

Claim 27

Dependent Claim 57 words

The method of claim 22 , wherein the capacitor plate is polysilicon and step (d) of forming the capacitor plate comprises the steps of: i) forming a dielectric layer on the sidewalls of said first trenches; ii) filling the first trenches with polysilicon; and iii) etching said polysilicon into said first trenches partially through said BOX layer.

Claim 28

Dependent Claim 29 words

The method of claim 24 , wherein step d of recessing the BOX layer comprises etching recesses into BOX layer sidewalls of said first trenches above said polysilicon plates.

Claim 29

Dependent Claim 53 words

The method of claim 25 , wherein the step (e) of forming the conductive straps comprises the steps of: i) depositing a layer of polysilicon; and ii) etching excess said polysilicon layer, straps remaining in said recesses and in contact with said capacitor plates and a bottom surface of said surface silicon layer.

Claim 30

Dependent Claim 25 words

The method of claim 26 , wherein before the step (i) of forming polysilicon layer, an oxidation of nitride is formed on exposed silicon surfaces.

Claim 31

Dependent Claim 70 words

The method of claim 26 , wherein the conductive gate material is polysilicon and the step (g) of filling the trenches with polysilicon comprises: i) forming a trench top oxide layer on said capacitor plates; ii) depositing a polysilicon layer of sufficient thickness to fill said first trenches; and iii) removing said polysilicon layer from an upper surface of said silicon layer, polysilicon remaining in and filling said first trenches.

Claim 32

Dependent Claim 22 words

A method of claim 28 wherein after the step (h) of forming second trenches said second trenches are filled with dielectric material.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2005-07-29	2006-01-28	2006-07-30	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2009-07-29	2010-01-28	2010-07-30	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2013-07-29	2014-01-28	2014-07-30	$7700.00	Window Closed / Lapsed

Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap

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