Manufacturing method of DRAM Cell formed on an insulating layer having a vertical channel

Claim 1

A method for preparing a semiconductor device having a plurality of memory cells in a matrix array, wherein each memory cell has a transistor and a capacitor and the transistor includes a vertical channel, which comprises the steps of: (a) forming a plurality of first junction regions on a first semiconductor wafer, each first junction region surrounded by a isolation layer; (b) forming a plurality of cylindrical charge storage electrodes, each cylindrical charge storage electrode containing side surfaces, an upper portion and a lower portion, and the upper portion of the cylindrical charge storage electrode coupled to a corresponding first junction region; (c) forming a dielectric layer over the side surfaces and lower surface of each of the cylindrical charge storage electrode; (d) forming a plate electrode surrounding an entire surface of the dielectric layer for said each cylindrical charge storage electrode; (e) forming a first insulation layer on the plate electrode by making a surface of the plate electrode flat; (f) bounding a second semiconductor wafer to the first insulation layer whereby the first semiconductor wafer is supported by the second semiconductor wafer; (g) forming a plurality of vertical channels by polishing and selectively etching the first semiconductor wafer having a thickness, each vertical channel coupled to the corresponding first junction region; (h) forming a gate electrode surrounding said each vertical channel, wherein the gate electrode has a gate insulator located between the gate electrode and said each vertical channel; (i) forming a second junction region on a upper surface of said each vertical channel; (j) forming a number of bit line by forming and selectively etching a second insulation layer on a resultant structure from the steps (a) to (i) and forming and selectively etching a metal layer over the etched second insulation layer, each bit line coupled to a predetermined number of the second junction regions arranged on a line.

Claim 2

A method for preparing a semiconductor device having a plurality of memory cells in a matrix array, wherein each memory cell has a transistor and a capacitor and the transistor includes a vertical channel, which comprises the steps of: (a) forming a plurality of first junction regions on a first semiconductor wafer, each first junction region surrounded by a isolation layer; (b) forming a plurality of cylindrical charge storage electrodes, each cylindrical charge storage electrode containing side surfaces, an upper portion and a lower portion, and the upper portion of the cylindrical charge storage electrode coupled to a corresponding first junction region; (c) forming a dielectric layer over the side surfaces and lower surface of each of the cylindrical charge storage electrode; (d) forming a plate electrode surrounding an entire surface of the dielectric layer for said each cylindrical charge storage electrode; (e) forming a first insulation layer on the plate electrode by making a surface of the plate electrode flat; (f) bounding a second semiconductor wafer to the first insulation layer whereby the first semiconductor wafer is supported by the second semiconductor wafer; (g) forming a plurality of vertical channels by polishing and selectively etching the first semiconductor wafer having a thickness, each vertical channel coupled to the corresponding first junction region; (h) forming a gate electrode surrounding said each vertical channel, wherein the gate electrode has a gate insulator located between the gate electrode and said each vertical channel; (i) forming a second junction region on a upper surface of said each vertical channel; (j) forming a number of bit line by forming and selectively etching a second insulation layer on a resultant structure from the steps (a) to (i) and forming and selectively etching a metal layer over the etched second insulation layer, each bit line coupled to a predetermined number of the second junction regions arranged on a line.