US5710056A
Expired / Lapsed
US
⏱️ 0.0 years remaining
DRAM with a vertical channel structure and process for manufacturing the same
Assignee: United Microelectronics Corp
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Filing: 1996-09-06
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Granted: 1998-01-20
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Expires: 2016-09-06
Abstract
Abstract A DRAM with a vertical channel structure is manufactured with an epitaxial silicon layer, above a silicon substrate, and is preformed with a source region. A well is formed in the epitaxial silicon layer. A trench is formed to penetrate into the source region. A first insulating layer is formed on a surface of the trench and then a gate is formed, almost completely filling up the remaining space in the trench. A drain region is formed inside the well. A storage capacitor is formed above the drain region.
Inventors
- 👤 Chen-Chung Hsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:03
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/34; H10B12/31
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
197 words
A method of fabricating a DRAM with a vertical channel structure, comprising the steps of: (a) forming a source region on top of a silicon substrate; (b) forming an epitaxial silicon layer above the source region; (c) defining active regions in the epitaxial silicon layer; (d) on a surface of the epitaxial silicon layer, forming a field oxide layer having a bird's beak structure, just outside the active area; (e) using the field oxide layer as a mask, forming a well such that a bottom of the well is in contact with a top surface of the source region; (f) forming a trench passing through at least the well to at least a top surface of the source region; (g) forming a first insulating layer on interior sidewalls and a bottom surface of the trench, and forming a gate that almost completely fills a remaining space in the trench; (h) in the well, forming a drain region lying between one edge of the gate and a remote edge of the bird's beak structure; (i) forming a second insulating layer with a contact window above the drain region; and; (j) forming a storage capacitor above the contact window.
Claim 2
Independent Claim
197 words
A method of fabricating a DRAM with a vertical channel structure, comprising the steps of: (a) forming a source region on top of a silicon substrate; (b) forming an epitaxial silicon layer above the source region; (c) defining active regions in the epitaxial silicon layer; (d) on a surface of the epitaxial silicon layer, forming a field oxide layer having a bird's beak structure, just outside the active area; (e) using the field oxide layer as a mask, forming a well such that a bottom of the well is in contact with a top surface of the source region; (f) forming a trench passing through at least the well to at least a top surface of the source region; (g) forming a first insulating layer on interior sidewalls and a bottom surface of the trench, and forming a gate that almost completely fills a remaining space in the trench; (h) in the well, forming a drain region lying between one edge of the gate and a remote edge of the bird's beak structure; (i) forming a second insulating layer with a contact window above the drain region; and; (j) forming a storage capacitor above the contact window.
Claim 3
Dependent Claim
33 words
A method according to claim 1, wherein the silicon substrate and the well are of the P-type, whereas the source region, the drain region and the epitaxial silicon layer are of the N-type.
Claim 4
Dependent Claim
53 words
A method according to claim 1, wherein said step (b) comprises the step of depositing the epitaxial layer to a thickness of about 2 μm under a pressure of about 50 Torr and a temperature of about 950° C., using SiH 2 Cl 2 , H 2 , and HCl as reactive gases.
Claim 5
Dependent Claim
60 words
A method according to claim 1, wherein said step (j) of forming the storage capacitor includes the steps of: forming a storage electrode of at least a second polysilicon layer, above the first contact window; forming a dielectric layer above the second polysilicon layer; and forming an opposed electrode of at least a third polysilicon layer, above the dielectric layer.
Claim 6
Dependent Claim
18 words
A method according to claim 4, wherein the second polysilicon layer has a thickness of about 3000-5000 Å.
Claim 7
Dependent Claim
14 words
A method according to claim 4, wherein the dielectric layer is an oxide/nitride/oxide layer.
Claim 8
Dependent Claim
26 words
A method according to claim 4, wherein the third polysilicon layer has a thickness of about 1000-2000 Å, and is doped by a phosphorus dopant source.
Claim 9
Dependent Claim
40 words
A method according to claim 1, further comprising the following steps performed after said step (j): depositing a borophosphosilicate glass layer by chemical vapor deposition; and planarizing the borophosphosilicate glass by heat fluidization at a temperature of about 850°-9500° C.
Claim 10
Dependent Claim
39 words
A method according to claim 2, wherein said step (a) includes forming the source region by implanting arsenic ions at an energy of about 50-100 KeV to provide a dosage of about 1×10 15 -1×10 16 atoms/cm 2 .
Claim 11
Dependent Claim
37 words
A method according to claim 2, wherein said step of forming a well includes implanting boron ions at an energy of about 100-200 KeV to provide a dosage of about 1×10 13 -1×10 14 atoms/cm 2 .
Claim 12
Dependent Claim
38 words
A method according to claim 2, wherein said step of forming the drain region includes implanting arsenic ions at an energy of about 50-100 KeV to provide a dosage of about 1×10 15 -1×10 16 atoms/cm 2 .
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-01-19 | 2001-07-21 | 2002-01-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-19 | 2005-07-21 | 2006-01-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-01-19 | 2009-07-21 | 2010-01-20 | $7700.00 | Window Closed / Lapsed |